EFM32WG Datasheet, PDF (339/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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6. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register.
7. Enter EM2.
Host Mode Sessions Start (SRP) (EM2 -> EM0)
Sequence of operations:
1. The core detects SRP (data line pulsing) on the bus. The core de-asserts the suspend_n signal to
the PHY, generating the PHY clock. The SRP Detected interrupt is generated.
2. The application clears the Stop PHY Clock bit, the core deasserts the suspend_n signal to the PHY
to generate the PHY clock.
3. The power (VDD_DN) is turned on and stabilizes.
4. The application clears the Power Clamp bit.
5. The application clears the Reset to Power-Down Modules bit.
6. The application programs the CSRs, and sets the Port Power bit to turn on VBUS.
7. The core detects device connection and drives a USB reset.
The core enters normal operating mode.
15.4.8.2.1.3 EM2 when the Core is in Device Mode
Device Mode Suspend With EM2
In Device mode, the device validates the host-driven Resume signal for a period of 1.5 µs (75 clock
cycles at 48 MHz). With a 32-KHz clock, 2.34 ms is required (75 clock cycles at 32 KHz) to detect the
resume. Hence, the application programs USB_DCFG.RESVALID with a value of 4 clock cycles (125
µs). If the core is in Suspend mode, the device thus detects the resume and the host signals a resume
for a minimum of 125 µs.
If the device is being reset from suspend, it begins a high-speed detection handshake after detecting
SE0 for no fewer than 2.5 µs. With a 48-MHz clock, detection occurs after 120 clock cycles (2.5 µs).
With a 32-kHz clock, 120 clock cycles signifies 3.75 msec. Hence, a programmable value of 4 clock
cycles (125 µs) is used to detect reset.
The 32-KHz Suspend feature incorporates switching to the 32-KHz clock during suspend and resume/
remote wakeup until the system comes up and starts driving 48 MHz.
Sequence of operations:
1. Detect Suspend state. Wait for an interrupt from the device core and check that
USB_GINTSTS.USBSUSP is set to 1.
2. Back up the essential registers of the core. Read and store the following core registers:
• USB_GINTMSK
• USB_GOTGCTL
• USB_GAHBCFG
• USB_GUSBCFG
• USB_GRXFSIZ
• USB_GNPTXFSIZ
• USB_DCFG
• USB_DCTL
• USB_DAINTMSK
• USB_DIEPMSK
• USB_DOEPMSK
• USB_DIEPx_CTL
• USB_DIEPx_TSIZ
• USB_DIEPx_DMAADDR
• USB_PCGCCTL
• USB_DIEPTXFn
3. The application sets the PWRCLMP bit in the Power and Clock Gating Control (USB_PCGCCTL)
register.
4. The application sets the USB_PCGCCTL.RSTPDWNMODULE bit.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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