EFM32WG Datasheet, PDF (244/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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In this configuration, the VREGO sense circuit should be left disabled.
Figure 15.7. Host
3.0V – 3.6V
VDD
USB_VREGI
USB_VREGO
EFM3 2
GPIO (over-current )
USB_VBUSEN
5V step-up
OC ^Vin
EN _Vout
USB_VBUS
USB_DP
USB_DM
VBUS
D+
D-
GND
15.3.3 PHY
The USB includes an internal full-speed/low-speed PHY with built-in pull-up/pull-down resistors, VBUS
comparators and ID line state sensing. During suspend, the PHY enters a low-power state where only
the single-ended receivers are active. The PHY is disabled by default and should be enabled by setting
PHYPEN in USB_ROUTE before the USB core clock is enabled.
The PHY is powered by the internal voltage regulator output (USB_VREGO). To power the PHY
directly from an external source (for example an external 3.3 V LDO), connect both USB_VREGO and
USB_VREGI to the external 3.3 V supply voltage. To stop the quiescent current present with the voltage
regulator enabled in this configuration, disable the the regulator by setting VREGDIS in USB_CTRL after
power up. Then the regulator is effectively bypassed.
When VREGO Sense is enabled, the PHY is automatically disabled internally when the VREGO Sense
output is low. This will happen if VBUS-power disappears. The application can detect this by keeping
the VREGO Sense Low Interrupt enabled. Note that PHYPEN in USB_ROUTE will not be set to 0 in
this case.
15.3.4 Voltage Regulator
The voltage regulator is used to regulate the 5 V VBUS voltage down to 3.3 V which is the operating
voltage for the PHY.
A decoupling capacitor is required on USB_VREGI and USB_VREGO. Note that the USB standard
requires the total capacitance on VBUS to be 1 uF minimum and 10 uF maximum for regular devices.
OTG devices can have maximum 6.5 uF capacitance on VBUS.
The voltage regulator is enabled by default and can thus be used to power the EFM32 itself. Systems not
using the USB should disable the regulator by setting VREGDIS in USB_CTRL. A voltage sense circuit
monitors the output voltage and can be used to detect when the voltage regulator becomes active. This
sense circuit can also be used to detect when the voltage drops (typically due to the USB cable being
unplugged). If regulator voltage monitoring is not required (i.e. it is known that the VREGO voltage is
always present), the sense circuit should be left disabled.
During suspend, the bias current for the regulator can be reduced if the current requirements in EM2/3 are
low. The bias current in EM2/3 is controlled by BIASPROGEM23 in USB_CTRL. When EM2/3 is entered,
the bias current for the regulator switches to what is specified in BIASPROGEM23 in USB_CTRL. When
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