EFM32WG Datasheet, PDF (249/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Send/Receive USB Transfers -> Soft disconnect->Soft reset->USB Device Enumeration
Sequence of operations:
1. The application configures the device to send or receive transfers.
2. The application sets the Soft disconnect bit (SFTDISCON) in the Device Control Register
(USB_DCTL).
3. The application sets the Soft Reset bit (CSFTRST) in the Reset Register (USB_GRSTCTL).
4. Poll the USB_GRSTCTL register until the core clears the soft reset bit, which ensures the soft reset
is completed properly.
5. Initialize the core according to the instructions in Device Initialization (p. 247) .
Suspend-> Soft disconnect->Soft reset->USB Device Enumeration
Sequence of operations:
1. The core detects a USB suspend and generates a Suspend Detected interrupt.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register, the core
puts the PHY in suspend mode, and the PHY clock stops.
3. The application clears the Stop PHY Clock bit in the Power and Clock Gating Control register, and
waits for the PHY clock to come back. The core takes the PHY back to normal mode, and the PHY
clock comes back.
4. The application sets the Soft disconnect bit (SFTDISCON) in Device Control Register (USB_DCTL).
5. The application sets the Soft Reset bit (CSFTRST) in the Reset Register (USB_GRSTCTL).
6. Poll the USB_GRSTCTL register until the core clears the soft reset bit, which ensures the soft reset
is completed properly.
7. Initialize the core according to the instructions in Device Initialization (p. 247) .
15.4.2 Modes of operation
• Overview: DMA/Slave modes (p. 249)
• DMA Mode (p. 249)
• Slave Mode (p. 250)
15.4.2.1 Overview: DMA/Slave modes
The application can operate the core in either of two modes:
• In DMA Mode (p. 249) - The core fetches the data to be transmitted or updates the received data
on the AHB.
• In Slave Mode (p. 250) — The application initiates the data transfers for data fetch and store.
15.4.2.2 DMA Mode
In DMA Mode, the OTG host uses the AHB master Interface for transmit packet data fetch (AHB to
USB) and receive data update (USB to AHB). The AHB master uses the programmed DMA address
(USB_HCx_DMAADDR register in host mode and USB_DIEPx_DMAADDR/USB_DOEPx_DMAADDR
register in device mode) to access the data buffers.
15.4.2.2.1 Transfer-Level Operation
In DMA mode, the application is interrupted only after the programmed transfer size is transmitted or
received (provided the core detects no NAK/Timeout/Error response in Host mode, or Timeout/CRC
Error in Device mode). The application must handle all transaction errors. In Device mode, all the USB
errors are handled by the core itself.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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