EFM32WG Datasheet, PDF (341/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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9. Wait for remote wakeup time (1-15ms) and then program USB_DCTL by performing read-modify-
write to set USB_DCTL.RMTWKUPSIG = 0.
Device Mode Session End (EM0 -> EM2)
Sequence of operations:
1. The core detects a USB suspend and generates a Suspend Detected interrupt. The host turns off
VBUS.
2. The application sets the Power Clamp bit in the Power and Clock Gating Control register.
3. The application sets the Reset to Power-Down Modules bit in the Power and Clock Gating Control
register.
4. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register.
5. Switch USB Core clock (USBC) to 32 kHz.
6. Enter EM2.
Device Mode Session Start (EM2 -> EM0)
Sequence of operations:
1. The core detects VBUS on (voltage level within session-valid). A New Session Detected interrupt is
generated.
2. Switch USB Core clock (USBC) back to 48 MHz.
3. The application clears the Stop PHY Clock bit.
4. The application clears the Power Clamp bit.
5. The application clears the Reset to Power-Down Modules bit.
6. The application programs CSRs.
7. The cores detects a USB reset.
The core enters normal operating mode.
15.4.8.2.2 Using Clock Gating in EM0/EM1
The core supports HCLK gating to reduce dynamic power to internal modules to the core during Suspend/
session-off state in EM0 and EM1.
15.4.8.2.2.1 Internal Clock Gating when the Core is in Host Mode
The following sections show the procedures you must follow to use the clock gating feature.
Host Mode Suspend and Resume With Clock Gating
Sequence of operations:
1. The application sets the Port Suspend bit in the Host Port CSR, and the core drives a USB suspend.
2. The application sets the Stop PHY Clock bit in the Power and Clock Gating Control register. The
application sets the Gate hclk bit in the Power and Clock Gating Control register, the core gates the
hclk internally.
3. The core remains in Suspend mode.
4. The application clears the Gate hclk and Stop PHY Clock bits, and the PHY clock is generated.
5. The application sets the Port Resume bit, and the core starts driving Resume signaling.
6. The application clears the Port Resume bit after at least 20 ms.
7. The core is in normal operating mode.
Host Mode Suspend and Remote Wakeup With Clock Gating
Sequence of operations:
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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