EFM32WG Datasheet, PDF (415/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
master wishes to read from or write to the slave. The second byte contains the eight least significant
bits of the slave address.
When a slave receives a 10-bit address, it must acknowledge both the address bytes if they match the
address of the slave.
When performing a master transmitter operation, the master transmits the two address bytes and then
the remaining data, as shown in Figure 16.8 (p. 415) .
Figure 16.8. I²C Master Transmitter/Slave Receiver with 10-bit Address
S
ADDR (1st 7 bits) W A
Addr (2nd byte)
A
DATA
AP
When performing a master receiver operation however, the master first transmits the two address bytes
in a master transmitter operation, then sends a repeated START followed by the first address byte and
then receives data from the addressed slave. The slave addressed by the 10-bit address in the first two
address bytes must remember that it was addressed, and respond with data if the address transmitted
after the repeated start matches its own address. An example of this (with one byte transmitted) is shown
in Figure 16.9 (p. 415) .
Figure 16.9. I²C Master Receiver/Slave Transmitter with 10-bit Address
S
ADDR (1st 7 bits) W A
Addr (2nd byte)
A Sr
ADDR (1st 7 bits) R A
DATA
NP
16.3.1.5 Arbitration, Clock Synchronization, Clock Stretching
Arbitration and clock synchronization are features aimed at allowing multi-master buses. Arbitration
occurs when two devices try to drive the bus at the same time. If one device drives it low, while the
other drives it high, the one attempting to drive it high will not be able to do so due to the open-drain
bus configuration. Both devices sample the bus, and the one that was unable to drive the bus in the
desired direction detects the collision and backs off, letting the other device continue communication
on the bus undisturbed.
Clock synchronization is a means of synchronizing the clock outputs from several masters driving the
bus at once, and is a requirement for effective arbitration.
Slaves on the bus are allowed to force the clock output on the bus low in order to pause the
communication on the bus and give themselves time to process data or perform any real-time tasks they
might have. This is called clock stretching.
Arbitration is supported by the I²C module for both masters and slaves. Clock synchronization and clock
stretching is also supported.
16.3.2 Enable and Reset
The I²C is enabled by setting the EN bit in the I2Cn_CTRL register. Whenever this bit is cleared, the
internal state of the I²C is reset, terminating any ongoing transfers.
Note
When re-enabling the I²C, the ABORT command or the Bus Idle Timeout feature must be
applied prior to use even if the BUSY flag is not set.
16.3.3 Safely Disabling and Changing Slave Configuration
The I²C slave is partially asynchronous, and some precautions are necessary to always ensure a safe
slave disable or slave configuration change. These measures should be taken, if (while the slave is
enabled) the user cannot guarantee that an address match will not occur at the exact time of slave
disable or slave configuration change.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
415
www.energymicro.com