EFM32WG Datasheet, PDF (67/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Description
b000000001 = 2 DMA transfers
b000000010 = 3 DMA transfers
b000000011 = 4 DMA transfers
b000000100 = 5 DMA transfers
.
.
.
b111111111 = 1024 DMA transfers.
The controller updates this field immediately prior to it entering the arbitration process. This
enables the controller to store the number of outstanding DMA transfers that are necessary to
complete the DMA cycle.
[3]
next_useburst Controls if the chnl_useburst_set [C] bit is set to a 1, when the controller is performing a
peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure.
Note
Immediately prior to completion of the DMA cycle that the alternate data structure
specifies, the controller sets the chnl_useburst_set [C] bit to 0 if the number of
remaining transfers is less than 2^R. The setting of the next_useburst bit controls if the
controller performs an additional modification of the chnl_useburst_set [C] bit.
In peripheral scatter-gather DMA cycle then after the DMA cycle that uses the alternate data
structure completes , either:
0 = the controller does not change the value of the chnl_useburst_set [C] bit. If the
chnl_useburst_set [C] bit is 0 then for all the remaining DMA cycles in the peripheral scatter-
gather transaction, the controller responds to requests on dma_req[ ] and dma_sreq[ ],
when it performs a DMA cycle that uses an alternate data structure.
1 = the controller sets the chnl_useburst_set [C] bit to a 1. Therefore, for the remaining DMA
cycles in the peripheral scatter-gather transaction, the controller only responds to requests on
dma_req[ ], when it performs a DMA cycle that uses an alternate data structure.
[2:0]
cycle_ctrl
The operating mode of the DMA cycle. The modes are:
b000
b001
b010
b011
b100
Stop. Indicates that the data structure is invalid.
Basic. The controller must receive a new request, prior to it entering the arbitration
process, to enable the DMA cycle to complete.
Auto-request. The controller automatically inserts a request for the appropriate channel
during the arbitration process. This means that the initial request is sufficient to enable
the DMA cycle to complete.
Ping-pong. The controller performs a DMA cycle using one of the data structures. After
the DMA cycle completes, it performs a DMA cycle using the other data structure. After
the DMA cycle completes and provided that the host processor has updated the original
data structure, it performs a DMA cycle using the original data structure. The controller
continues to perform DMA cycles until it either reads an invalid data structure or the
host processor changes the cycle_ctrl bits to b001 or b010. See Section 8.4.2.3.4 (p.
55) .
Memory scatter/gather. See Section 8.4.2.3.5 (p. 57) .
When the controller operates in memory scatter-gather mode, you must only use this
value in the primary data structure.
b101 Memory scatter/gather. See Section 8.4.2.3.5 (p. 57) .
When the controller operates in memory scatter-gather mode, you must only use this
value in the alternate data structure.
b110 Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 60) .
When the controller operates in peripheral scatter-gather mode, you must only use this
value in the primary data structure.
b111 Peripheral scatter/gather. See Section 8.4.2.3.6 (p. 60) .
When the controller operates in peripheral scatter-gather mode, you must only use this
value in the alternate data structure.
At the start of a DMA cycle, or 2^R DMA transfer, the controller fetches the channel_cfg from system
memory. After it performs 2^R, or N, transfers it stores the updated channel_cfg in system memory.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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