EFM32WG Datasheet, PDF (391/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Offset
0x3C920
Reset
Access
Name
...the world's most energy friendly microcontrollers
Bit Position
Bit
31
30
29
28
27
26
25:22
21
20
19:18
17
Name
Reset
Access Description
EPENA
0
RW1
Endpoint Enable
In DMA mode for IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint. The core clears this bit before
setting any of the following interrupts on this endpoint: SETUP Phase Done, Endpoint Disabled, Transfer Completed. For control
endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.
EPDIS
0
RW1
Endpoint Disable
The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete.
The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before
setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.
SETD1PIDOF
0
W1
Set DATA1 PID / Odd Frame
For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register
to DATA1ODD.
For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA1ODD).
SETD0PIDEF
0
W1
Set DATA0 PID / Even Frame
For bulk and interrupt endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field in this register
to DATA0EVEN.
For isochronous endpoints writing this field sets the Endpoint Data PID / Even or Odd Frame (DPIDEOF) field to odd (DATA0EVEN).
SNAK
0
W1
Set NAK
A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes
on an endpoint. The core can also set this bit for an endpoint after a SETUP packet is received on that endpoint.
CNAK
0
W1
Clear NAK
A write to this bit clears the NAK bit for the endpoint.
TXFNUM
0x0
RW
TxFIFO Number
These bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO
number. This field is valid only for IN endpoints.
STALL
0
RW1
Handshake
For bulk and interrupt endpoints: The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global
Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. In this case only the application
can clear this bit, never the core.
When control endpoint: The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint.
If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of
this bit's setting, the core always responds to SETUP data packets with an ACK handshake.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
EPTYPE
0x0
RW
This is the transfer type supported by this logical endpoint.
Endpoint Type
Value
0
1
2
3
Mode
CONTROL
ISO
BULK
INT
Description
Control Endpoint.
Isochronous Endpoint.
Bulk Endpoint.
Interrupt Endpoint.
NAKSTS
0
R
NAK Status
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
391
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