EFM32WG Datasheet, PDF (568/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

...the world's most energy friendly microcontrollers
Low power mode is only available when using LFXO or LFRCO.
22.3.7 Retention Registers
The Backup RTC includes 128 x 32 bit registers with possible retention in all energy modes. The registers
are accessible through the RETx_REG registers. Retention is by default enabled in EM0 through EM4.
The registers can be shut off to save power by setting RAM in BURTC_POWERDOWN. Note that the
retention registers cannot be accessed when RSTEN in BURTC_CTRL is set.
Note
The retention registers are mapped to a RAM instance and have undefined state out of
reset.
If the system should lose main power and enter backup mode while writing to the retention registers,
the RAM write error flag, RAMWERR, in BURTC_STATUS will be set, and the attempted write will be
canceled. The RAMWERR flag is cleared by writing a 1 to CLRSTATUS in BURTC_CMD.
22.3.8 Backup operation
The Backup RTC and the retention registers reside in a separate power domain, which in addition to
being available in EM4 has the possibility to be powered by a backup battery. Refer to Section 10.3.4 (p.
111) for further details on this power domain.
22.3.9 Backup mode timestamp
The Backup RTC includes functionality for storing a timestamp when the system enters backup mode.
The timestamp is stored in the BURTC_TIMESTAMP register. If Low Power mode is enabled, ignored
bits will not be stored in the timestamp register. Timestamping is enabled by setting BUMODETSEN
in BURTC_CTRL. When a timestamp is stored, the BUMODETS bit in BUCTRL_STATUS is set. To
prevent uncontrolled time stamping when entering and exiting backup mode, this status bit has to be
cleared before a new timestamp can be stored. Writing a 1 to CLRSTATUS in BURTC_CMD clears
BUMODETS.
22.3.10 LFXO failure detection
To be able to detect LFXO failure, the Backup RTC includes a five bit down counter with configurable
top value. The top value is configured in TOP in BURTC_LFXOFDET. The counter starts at the top
value and counts downwards on either LFRCO or ULFRCO, depending on the configuration of OSC
in BURTC_LFXOFDET. When LFRCO is selected as clock for the down counter, it will be prescaled
with a factor of 2^{PRESC + LPCOMP}. The counter wraps to TOP when it reaches zero. If no LFXO clock has
arrived since the last time the counter reached zero , the BURTC clock is changed to the clock source
configured in OSC and the LFXOFAIL interrupt flag is set. Note that due to synchronization, the LFXO
clock needs to arrive at least two cycles before the counter reaches zero.
22.3.11 Register access
Most Backup RTC configuration should not be changed while the counter is running, i.e. they should
only be changed while RSTEN in BURTC_CTRL is set.
Registers allowed to change run-time are BURTC_COMP0, BURTC_LPMODE, and DEBUGRUN in
BURTC_CTRL. For further details on access to these registers, refer to Section 5.3 (p. 21) .
Note
The Backup domain has its own reset signal which is active when the device powers up for
the first time. The reset is deactivated by clearing BURSTEN in RMU_CTRL. This has to be
done before any registers in the Backup RTC can be accessed.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
568
www.energymicro.com