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15.4.4.2.2.10 Generic Interrupt OUT Data Transfers Using Periodic Transfer Interrupt Feature
This section describes a regular INTR OUT data transfer with the Periodic Transfer Interrupt feature.
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the host, it must initialize an endpoint
as described in Endpoint Initialization (p. 281) . See Packet Read from FIFO in Slave Mode (p. 290) .
Application Requirements
1. Before setting up a periodic OUT transfer, the application must allocate a buffer in the memory to
accommodate all data to be received as part of the OUT transfer, then program that buffer’s size and
start address in the endpoint-specific registers.
2. For Interrupt OUT transfers, the Transfer Size field in the endpoint’s Transfer Size register must be a
multiple of the maximum packet size of the endpoint, adjusted to the DWORD boundary. The Transfer
Size programmed can span across multiple frames based on the periodicity after which the application
want to receive the USB_DOEPx_INT.XFERCOMPL interrupt
• transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4))
• packet count[epnum] = n
• n > 0 (Higher value of n reduces the periodicity of the USB_DOEPx_INT.XFERCOMPL interrupt)
• 1 < packet count[epnum] < n (Higher value of n reduces the periodicity of the
USB_DOEPx_INT.XFERCOMPL interrupt)
3. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD
boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte pads
at end of a maximum-packet-size packet up to the end of the DWORD. The application will not be
informed about the frame number on which a specific packet has been received.
4. On USB_DOEPx_INT.XFERCOMPL interrupt, the application must read the endpoint’s Transfer Size
register to calculate the size of the payload in the memory. The received payload size can be less
than the programmed transfer size.
• Payload size in memory = application-programmed initial transfer size – core updated final transfer
size
• Number of USB packets in which this payload was received = application-programmed initial packet
count – core updated final packet count.
• If for some reason, the host stops sending tokens, there are no interrupts to the application, and
the application must timeout on its own.
5. The assertion of the USB_DOEPx_INT.XFERCOMPL interrupt marks the completion of the interrupt
OUT data transfer. This interrupt does not necessarily mean that the data in memory is good.
6. Read the USB_DOEPx_TSIZ register to determine the size of the received transfer and to determine
the validity of the data received in the frame.
Internal Data Flow
1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers,
clear the NAK bit, and enable the endpoint to receive the data.
• The application must enable the USB_DCTL.IGNRFRMNUM
2. When an interrupt OUT endpoint is enabled by setting the Endpoint Enable and clearing the NAK
bits, the Even/Odd frame will be ignored by the core.
1. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long
as there is space in the receive FIFO. For every data packet received on the USB, the data packet
and its status are written to the receive FIFO. Every packet (maximum packet size or short packet)
written to the receive FIFO decrements the Packet Count field for that endpoint by 1.
• OUT data packets received with Bad Data CRC or any packet error are flushed from the receive
FIFO automatically.
• Interrupt packets with PID errors are not passed to application. Core discards the packet, sends
ACK and does not decrement packet count.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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