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EFM32WG Datasheet, PDF (517/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.
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Bit
Name
Reset
Access Description
Set when the value written to TXDATA is being synchronized.
5
TXDATAX
0
R
TXDATAX Register Busy
Set when the value written to TXDATAX is being synchronized.
4
SIGFRAME
0
R
SIGFRAME Register Busy
Set when the value written to SIGFRAME is being synchronized.
3
STARTFRAME
0
R
STARTFRAME Register Busy
Set when the value written to STARTFRAME is being synchronized.
2
CLKDIV
0
R
CLKDIV Register Busy
Set when the value written to CLKDIV is being synchronized.
1
CMD
0
R
CMD Register Busy
Set when the value written to CMD is being synchronized.
0
CTRL
0
R
CTRL Register Busy
Set when the value written to CTRL is being synchronized.
19.5.19 LEUARTn_ROUTE - I/O Routing Register
Offset
0x054
Reset
Access
Bit Position
Name
Bit
31:11
10:8
7:2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
LOCATION
0x0
RW
Decides the location of the LEUART I/O pins.
I/O Location
Value
0
1
2
3
4
Mode
LOC0
LOC1
LOC2
LOC3
LOC4
Description
Location 0
Location 1
Location 2
Location 3
Location 4
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TXPEN
0
RW
When set, the TX pin of the LEUART is enabled.
TX Pin Enable
Value
0
1
Description
The LEUn_TX pin is disabled
The LEUn_TX pin is enabled
RXPEN
0
RW
When set, the RX pin of the LEUART is enabled.
RX Pin Enable
Value
0
1
Description
The LEUn_RX pin is disabled
The LEUn_RX pin is enabled
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
517
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