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Figure 14.12. EBI Page Mode Read Operation for D16A16ALE addressing mode
EBI_AD[ 15:0]
EBI_ALE
EBI_CSn
EBI_REn
ADDRSETUP RDSETUP
(1, 2, 3, ...)
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDRSETUP RDSETUP
(1, 2, 3, ...)
(0, 1, 2, ...)
RDPA
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDR0
Z
DATA0
ADDR1
Z
DATA1
Z
Figure 14.13. EBI Page Mode Read Operation for D8A24ALE addressing mode
EBI_AD[ 15:8]
EBI_AD[ 7:0]
EBI_ALE
EBI_CSn
EBI_REn
ADDRSETUP
(0, 1, 2, ...)
RDSETUP
(0, 1, 2, ...)
ADDR0[ 23:16]
ADDR0[ 15:8]
RDSTRB
(1, 2, 3, ...)
ADDR0[ 7:0]
Z
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDR1[ 7:0] ADDR2[ 7:0] ADDR3[ 7:0]
Z
DATA0
DATA1
DATA2
DATA3
Z
Figure 14.14. EBI Page Mode Read Operation for D16 addressing mode
EBI_A[ N-1:0]
EBI_AD[ 15:0]
EBI_CSn
EBI_REn
RDSETUP
(0, 1, 2, ...)
ADDR0
Z
RDSTRB
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDR1
ADDR2
ADDR3
Z
DATA0
DATA1
DATA2
DATA3
Z
The maximum duration that a page is kept open is defined in the KEEPOPEN bitfield of the
EBI_PAGECTRL register. New read transactions which hit in an open page are started with RDPA
intrapage timing if the KEEPOPEN time has not been exceeded at the start of such a transaction. The
default setting of KEEPOPEN, which is equal to 0, will therefore never allow for intrapage timing to occur.
Transactions are allowed to finish if the KEEPOPEN time is exceeded during the transaction. Otherwise
the RDSTRB interpage timing is used for the read transaction. Next to exceeding the KEEPOPEN time
there are other reasons for closing an open page. In particular EBI transactions which result in a write or a
non-intrapage read always cause the page to be closed. Also the lack of a new EBI transaction will cause
an open page to be closed. In order to prevent this last scenario as much as possible read transactions
can often be made back to back. This is achieved by enabling prefetching by setting PREFETCH to 1
in the EBI_RDTIMING (or EBI_RDTIMINGn) register and by disallowing idle state insertion in between
transfers by setting the NOIDLE (or NOIDLEn) bit to 1 in EBI_CTRL register. Figure 14.15 (p. 180)
shows an example in which only ADDR1 benefits from intrapage timing because an unrelated AHB
transfer not directed at the EBI causes late arrival of ADDR2. ADDR2 arrives too late to be inserted as
a back to back read transfer. The page is considered closed and ADDR2 can therefore not benefit from
intrapage timing and it results in an interpage access instead.
Figure 14.15. EBI Page Closing
AHB ADDRESS
EBI_A[ N-1:0]
EBI_AD[ 15:0]
EBI_CSn
EBI_REn
ADDR0
RDSETUP
(0, 1, 2, ...)
ADDR1
ADDR0
Z
RDSTRB
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
NON-EBI
RDHOLD
(0, 1, 2, ...)
ADDR2
ADDR1
DATA0
DATA1
Z
IDLE
Z
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
ADDR2
14.3.6 Extended addressing
Extended addressing is used to extend the address range for any of the addressing modes described in
Section 14.3.4 (p. 178), Section 14.3.1 (p. 175), Section 14.3.2 (p. 176) and Section 14.3.3 (p.
177) . Up to 28 address bits can be individually enabled on the EBI_A address lines providing up to 256
MB of address space per memory bank. The operation on the EBI_AD lines is not affected by this. See
Section 14.3.12 (p. 185) for the memory map definitions related to the EBI. An example of address
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