EFM32WG Datasheet, PDF (71/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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8.4.7 Interrupts
The PL230 dma_done[n:0] signals (one for each channel) as well as the dma_err signal, are available as
interrupts to the Cortex-M4 core. They are combined into one interrupt vector, DMA_INT. If the interrupt
for the DMA is enabled in the ARM Cortex-M4 core, an interrupt will be made if one or more of the
interrupt flags in DMA_IF and their corresponding bits in DMA_IEN are set.
8.5 Examples
A basic example of how to program the DMA for transferring 42 bytes from the USART1 to
memory location 0x20003420. Assumes that the channel 0 is currently disabled, and that the
DMA_ALTCTRLBASE register has already been configured.
Example 8.1. DMA Transfer
1. Configure the channel select for using USART1 with DMA channel 0
a. Write SOURCESEL=0b001101 and SIGSEL=XX to DMA_CHCTRL0
2. Configure the primary channel descriptor for DMA channel 0
a. Write XX (read address of USART1) to src_data_end_ptr
b. Write 0x20003420 + 40 to dst_data_end_ptr c
c. Write these values to channel_cfg for channel 0:
i. dst_inc=b01 (destination halfword address increment)
ii. dst_size=b01 (halfword transfer size)
iii. src_inc=b11 (no address increment for source)
iv. src_size=01 (halfword transfer size)
v. dst_prot_ctrl=000 (no cache/buffer/privilege)
vi. src_prot_ctrl=000 (no cache/buffer/privilege)
vii.R_power=b0000 (arbitrate after each DMA transfer)
viii.n_minus_1=d20 (transfer 21 halfwords)
ix. next_useburst=b0 (not applicable)
x. cycle_ctrl=b001 (basic operating mode)
3. Enable the DMA
a. Write EN=1 to DMA_CONFIG
4. Disable the single requests for channel 0 (i.e., do not react to data available, wait for buffer full)
a. Write DMA_CHUSEBURSTS[0]=1
5. Enable buffer-full requests for channel 0
a. Write DMA_CHREQMASKC[0]=1
6. Use the primary data structure for channel 0
a. Write DMA_CHALTC[0]=1
7. Enable channel 0
a. Write DMA_CHENS[0]=1
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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