EFM32WG Datasheet, PDF (66/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
[25:24] src_size
[23:21] dst_prot_ctrl
[20:18] src_prot_ctrl
[17:14] R_power
[13:4] n_minus_1
Description
Source data width = byte
b00 = byte.
b01 = halfword.
b10 = word.
Source data width = halfword
b11 = no increment. Address remains set to the value that
the src_data_end_ptr memory location contains.
b00 = reserved.
b01 = halfword.
b10 = word.
Source data width = word
b11 = no increment. Address remains set to the value that
the src_data_end_ptr memory location contains.
b00 = reserved.
b01 = reserved.
b10 = word.
b11 = no increment. Address remains set to the value that
the src_data_end_ptr memory location contains.
Set the bits to match the size of the source data:
b00 = byte
b01 = halfword
b10 = word
b11 = reserved.
Set the bits to control the state of HPROT when the controller writes the destination data.
Bit [23]
Bit [22]
Bit [21]
This bit has no effect on the DMA.
This bit has no effect on the DMA.
Controls the state of HPROT as follows:
0 = HPROT is LOW and the access is non-privileged.
1 = HPROT is HIGH and the access is privileged.
Set the bits to control the state of HPROT when the controller reads the source data.
Bit [20]
Bit [19]
Bit [18]
This bit has no effect on the DMA.
This bit has no effect on the DMA.
Controls the state of HPROT as follows:
0 = HPROT is LOW and the access is non-privileged.
1 = HPROT is HIGH and the access is privileged.
Set these bits to control how many DMA transfers can occur before the controller re-arbitrates.
The possible arbitration rate settings are:
b0000
b0001
b0010
b0011
b0100
b0101
b0110
b0111
b1000
b1001
b1010 - b1111
Arbitrates after each DMA transfer.
Arbitrates after 2 DMA transfers.
Arbitrates after 4 DMA transfers.
Arbitrates after 8 DMA transfers.
Arbitrates after 16 DMA transfers.
Arbitrates after 32 DMA transfers.
Arbitrates after 64 DMA transfers.
Arbitrates after 128 DMA transfers.
Arbitrates after 256 DMA transfers.
Arbitrates after 512 DMA transfers.
Arbitrates after 1024 DMA transfers. This means that no arbitration occurs
during the DMA transfer because the maximum transfer size is 1024.
Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers
that the DMA cycle contains. You must set these bits according to the size of DMA cycle that
you require.
The 10-bit value indicates the number of DMA transfers, minus one. The possible values are:
b000000000 = 1 DMA transfer
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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