EFM32WG Datasheet, PDF (86/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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8.7.17 DMA_ERRORC - Bus Error Clear Register
Offset
0x04C
Reset
Access
Bit Position
Name
Bit
Name
Reset
Access Description
31:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
ERRORC
0
RW
Bus Error Clear
This bit is set high if an AHB bus error has occurred. Writing a 1 to this bit will clear the bit. If the error is deasserted at the same time
as an error occurs on the bus, the error condition takes precedence and ERRORC remains asserted.
8.7.18 DMA_CHREQSTATUS - Channel Request Status
Offset
0xE10
Reset
Access
Bit Position
Name
Bit
31:12
11
10
9
8
7
6
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CH11REQSTATUS
0
R
Channel 11 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
CH10REQSTATUS
0
R
Channel 10 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
CH9REQSTATUS
0
R
Channel 9 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
CH8REQSTATUS
0
R
Channel 8 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
CH7REQSTATUS
0
R
Channel 7 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
CH6REQSTATUS
0
R
Channel 6 Request Status
When this bit is 1, it indicates that the peripheral connected as the input to this DMA channel is requesting the controller to service
the DMA channel. The controller services the request by performing the DMA cycle using 2^R DMA transfers.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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