EFM32WG Datasheet, PDF (355/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Offset
0x3C008
Reset
Access
Name
...the world's most energy friendly microcontrollers
Bit Position
Bit
31:23
22
21
20:9
8
7
6
5
4:1
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
NOTIALLDMAWRIT
0
RW
Notify All DMA Writes
This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/
Endpoint. This bit is valid only when USB_GAHBCFG.REMMEMSUPP is set to 1. When set, the core asserts int_dma_req for all the
DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations.
The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/
Endpoint. When cleared, the core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a
particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete
the transfer of a particular Channel/Endpoint.
REMMEMSUPP
0
RW
Remote Memory Support
This bit is programmed to enable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers. When set, the
int_dma_req output signal is asserted when HSOTG DMA starts write transfer to the external memory. When the core is done with the
Transfers it asserts int_dma_done signal to flag the completion of DMA writes from HSOTG. The core then waits for sys_dma_done
signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint. When
cleared, the int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp
interrupt as soon as the DMA write transfer is done at the HSOTG Core Boundary and it doesn't wait for the sys_dma_done signal
to complete the DATA.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PTXFEMPLVL
0
RW
Periodic TxFIFO Empty Level (host only)
Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (USB_GINTSTS.PTXFEMP) is triggered. This
bit is used only in Slave mode.
Value
0
1
Mode
HALFEMPTY
EMPTY
Description
USB_GINTSTS.PTXFEMP interrupt indicates that the Periodic TxFIFO is half empty.
USB_GINTSTS.PTXFEMP interrupt indicates that the Periodic TxFIFO is completely
empty.
NPTXFEMPLVL
0
RW
Non-Periodic TxFIFO Empty Level (host and device)
This bit is used only in Slave mode. In host mode this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core
Interrupt register (USB_GINTSTS.NPTXFEMP) is triggered. In device mode, this bit indicates when IN endpoint Transmit FIFO empty
interrupt (USB_DIEP0INT/USB_DIEPx_INT.TXFEMP) is triggered.
Value
0
1
Mode
HALFEMPTY
EMPTY
Description
Host Mode: USB_GINTSTS.NPTXFEMP interrupt indicates that the Non-Periodic
TxFIFO is half empty.
Device Mode: USB_DIEP0INT/USB_DIEPx_INT.TXFEMP interrupt indicates that the
IN Endpoint TxFIFO is half empty.
Host Mode: USB_GINTSTS.NPTXFEMP interrupt indicates that the Non-Periodic
TxFIFO is completely empty.
Device Mode: USB_DIEP0INT/USB_DIEPx_INT.TXFEMP interrupt indicates that the
IN Endpoint TxFIFO is completely empty.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DMAEN
0
RW
DMA Enable (host and device)
When set to 0 the core operates in Slave mode. When set to 1 the core operates in a DMA mode.
HBSTLEN
0x0
RW
Burst Length/Type (host and device)
This field is used in DMA mode.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
355
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