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• PRS source 1, determined by DTPRS1FSEL in TIMER0_DTFC
• Debugger
• Core Lockup
One or two PRS channels can be used as an error source. When PRS source 0 is selected as an error
source, DTPRS0FSEL determines which PRS channel is used for this source. DTPRS1FSEL determines
which PRS channel is selected as PRS source 1. Please note that for Core Lockup, the LOCKUPRDIS
in RMU_CTRL must be set. Otherwise this will generate a full reset of the EFM32.
20.3.3.3.1 Action on Fault
When a fault occurs, the bit representing the fault source is set in DTFS, and the outputs from the DTI unit
are set to a well-defined state. The following options are available, and can be enabled by configuring
DTFACT in TIMER0_DTFC:
• Set outputs to inactive level
• Clear outputs
• Tristate outputs
With the first option enabled, the output state in case of a fault depends on the polarity settings for the
individual outputs. An output set to be active high will be set low if a fault is detected, while an output
set to be active low will be driven high.
When a fault occurs, the fault source(s) can be read out of TIMER0_DTFS. TIMER0_DTFS is organized
in the same way as DTFSEN, with one bit for each source.
20.3.3.3.2 Exiting Fault State
When a fault is triggered by the PRS system, software intervention is required to re-enable the outputs
of the DTI unit. This is done by manually clearing TIMER0_DTFS. If the fault cause, determined by
TIMER0_DTFS, is the debugger alone, the outputs can optionally be re-enabled when the debugger
exits and the processor resumes normal operation. The corresponding bit in TIMER0_DTFS will in that
case be cleared by hardware. The automatic start-up functionality can be enabled by setting DTDAS in
TIMER0_DTCTRL. If more bits are still set in DTFS when the automatic start-up functionality has cleared
the debugger bit, the DTI module does not exit the fault state. The fault state is only exited when all the
bits in TIMER0_DTFS have been cleared.
20.3.3.4 Configuration Lock
To prevent software errors from making changes to the DTI configuration, a configuration lock is
available. Writing any value but 0xCE80 to LOCKKEY in TIMER0_DTLOCK results in TIMER0_DTFC,
TIMER0_DTCTRL, TIMER0_DTTIME and TIMER0_ROUTE being locked for writing. To unlock the
registers, write 0xCE80 to LOCKKEY in TIMER0_DTLOCK. The value of TIMER0_DTLOCK is 1 when
the lock is active, and 0 when the registers are unlocked.
20.3.4 Debug Mode
When the CPU is halted in debug mode, the timer can be configured to either continue to run or to be
frozen. This is configured in DBGHALT in TIMERn_CTRL.
20.3.5 Interrupts, DMA and PRS Output
The Timer has 5 output events:
• Counter Underflow
• Counter Overflow
• Compare match or input capture (one per Compare/Capture channel)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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