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16.3 Functional Description
An overview of the I²C module is shown in Figure 16.1 (p. 412) .
Figure 16.1. I²C Overview
Peripheral Bus
I2 Cn _SD A
Pin
ctrl
I2 Cn _SCL
I²C Cont rol and
St at us
Sym bol
Generat or
Transm it Buffer
Transm it
Shift Regist er
Re c e i v e
Cont roller
Clock generat or
Receive Buffer
Re c e i v e
Shift Regist er
Address
Re c o g n i ze r
16.3.1 I²C-Bus Overview
The I²C-bus uses two wires for communication; a serial data line (SDA) and a serial clock line (SCL) as
shown in Figure 16.2 (p. 412) . As a true multi-master bus it includes collision detection and arbitration
to resolve situations where multiple masters transmit data at the same time without data loss.
Figure 16.2. I²C-Bus Example
V_DD
I²C m ast er
#1
I²C m ast er
#2
I²C slave
#1
I²C slave
#2
I²C slave
#3
R_p
SDA
SCL
Each device on the bus is addressable by a unique address, and an I²C master can address all the
devices on the bus, including other masters.
Both the bus lines are open-drain. The maximum value of the pull-up resistor can be calculated as a
function of the maximal rise-time tr for the given bus speed, and the estimated bus capacitance Cb as
shown in Equation 16.1 (p. 412) .
I²C Pull-up Resistor Equation
Rp(max) = (tr/0.8473) x Cb.
(16.1)
The maximal rise times for 100 kHz, 400 kHz and 1 MHz I²C are 1 µs, 300 ns and 120 ns respectively.
Note
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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