EFM32WG Datasheet, PDF (91/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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8.7.23 DMA_IEN - Interrupt Enable register
Offset
0x100C
Reset
Access
Bit Position
Name
Bit
31
30:12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reset
Access Description
ERR
0
RW
DMA Error Interrupt Flag Enable
Set this bit to enable interrupt on AHB bus error.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CH11DONE
0
RW
DMA Channel 11 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH10DONE
0
RW
DMA Channel 10 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH9DONE
0
RW
DMA Channel 9 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH8DONE
0
RW
DMA Channel 8 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH7DONE
0
RW
DMA Channel 7 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH6DONE
0
RW
DMA Channel 6 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH5DONE
0
RW
DMA Channel 5 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH4DONE
0
RW
DMA Channel 4 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH3DONE
0
RW
DMA Channel 3 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH2DONE
0
RW
DMA Channel 2 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH1DONE
0
RW
DMA Channel 1 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
CH0DONE
0
RW
DMA Channel 0 Complete Interrupt Enable
Write to 1 to enable complete interrupt on this DMA channel. Clear to disable the interrupt.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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