EFM32WG Datasheet, PDF (439/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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16.5.9 I2Cn_RXDATAP - Receive Buffer Data Peek Register
Offset
0x020
Bit Position
Reset
Access
Name
Bit
Name
Reset
Access Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7:0
RXDATAP
0x00
R
RX Data Peek
Use this register to read from the receive buffer. Buffer is not emptied on read access.
16.5.10 I2Cn_TXDATA - Transmit Buffer Data Register
Offset
0x024
Bit Position
Reset
Access
Name
Bit
Name
Reset
Access Description
31:8
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
7:0
TXDATA
0x00
W
TX Data
Use this register to write a byte to the transmit buffer.
16.5.11 I2Cn_IF - Interrupt Flag Register
Offset
0x028
Reset
Access
Bit Position
Name
Bit
31:17
16
15
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
SSTOP
0
R
Slave STOP condition Interrupt Flag
Set when a STOP condition has been received. Will be set regardless of the EFM32 being involved in the transaction or not.
CLTO
0
R
Clock Low Timeout Interrupt Flag
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
439
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