EFM32WG Datasheet, PDF (800/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Bit
Name
MUX
1
3
Reset
MUXE
1
1
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Access
Description
Mode
SEXTAPLEX
OCTAPLEX
Description
Sextaplex. Uses com lines LCD_COM0-
LCD_COM5.
Octaplex. Uses com lines LCD_COM0-
LCD_COM7.
33.5.3 LCD_SEGEN - Segment Enable Register
Offset
0x008
Bit Position
Reset
Access
Name
Bit
31:10
9:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
SEGEN
0x000
RW
Segment Enable
Determines which segment lines are enabled. Each bit represents a group of 4 segment lines. To enable segment lines X to X+3,
set bit X/4, i.e. to enable output on segment lines 4,5,6 and 7, set bit 1. Each LCD segment pin can also be individually disabled by
setting the pin to any other state than DISABLED in the GPIO pin configuration.
33.5.4 LCD_BACTRL - Blink and Animation Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x00C
Reset
Bit Position
Access
Name
Bit
31:29
28
27:24
23:18
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
ALOC
0
RW
Set the LCD segments which animation applies to
Animation Location
Value
0
1
Mode
SEG0TO7
SEG8TO15
Description
Animation appears on segments 0 to 7
Animation appears on segments 8 to 15
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
FCTOP
0x00
RW
Frame Counter Top Value
These bits contain the Top Value for the Frame Counter: CLK_EVENT = CLK_FC / (1 + FCTOP[5:0]).
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
800
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