EFM32WG Datasheet, PDF (636/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

Bit
Name
Reset
Value
1
2
3
Mode
PIN
ADCACMP
PINADCACMP
7:6
DACCH0OUT
0x0
Value
0
1
2
3
Mode
DISABLE
PIN
ADCACMP
PINADCACMP
5:4
DACCH1CONV
0x0
Value
0
1
2
3
Mode
DISABLE
CONTINUOUS
SAMPLEHOLD
SAMPLEOFF
3:2
DACCH0CONV
0x0
Value
0
1
2
3
Mode
DISABLE
CONTINUOUS
SAMPLEHOLD
SAMPLEOFF
1
DACCH1DATA
0
Configure DAC data control.
Value
0
1
Mode
DACDATA
ACMPTHRES
0
DACCH0DATA
0
Value
0
1
Mode
DACDATA
ACMPTHRES
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Access Description
Description
DAC CH1 output to pin enabled, output to ADC and ACMP disabled
DAC CH1 output to pin disabled, output to ADC and ACMP enabled
DAC CH1 output to pin, ADC, and ACMP enabled.
RW
DAC channel 0 output mode
Description
DAC CH0 output to pin and ACMP/ADC disabled
DAC CH0 output to pin enabled, output to ADC and ACMP disabled
DAC CH0 output to pin disabled, output to ADC and ACMP enabled
DAC CH0 output to pin, ADC, and ACMP enabled.
RW
DAC channel 1 conversion mode
Description
LESENSE does not control DAC CH1.
DAC channel 1 is driven in continuous mode.
DAC channel 1 is driven in sample hold mode.
DAC channel 1 is driven in sample off mode.
RW
DAC channel 0 conversion mode
Description
LESENSE does not control DAC CH0.
DAC channel 0 is driven in continuous mode.
DAC channel 0 is driven in sample hold mode.
DAC channel 0 is driven in sample off mode.
RW
DAC CH1 data selection.
Description
DAC data is defined by CH1DATA in the DAC interface.
DAC data is defined by ACMPTHRES in CHx_INTERACT.
RW
DAC CH0 data selection.
Description
DAC data is defined by CH0DATA in the DAC interface.
DAC data is defined by ACMPTHRES in CHx_INTERACT.
25.5.4 LESENSE_DECCTRL - Decoder control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x00C
Reset
Access
Bit Position
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
636
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