EFM32WG Datasheet, PDF (73/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

8.7 Register Description
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8.7.1 DMA_STATUS - DMA Status Registers
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31:21
20:16
15:8
7:4
3:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CHNUM
0x0B
R
Channel Number
Number of available DMA channels minus one.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
STATE
0x0
R
Control Current State
State can be one of the following. Higher values (11-15) are undefined.
Value
0
1
2
3
4
5
6
7
8
9
10
Mode
IDLE
RDCHCTRLDATA
RDSRCENDPTR
RDDSTENDPTR
RDSRCDATA
WRDSTDATA
WAITREQCLR
WRCHCTRLDATA
STALLED
DONE
PERSCATTRANS
Description
Idle
Reading channel controller data
Reading source data end pointer
Reading destination data end pointer
Reading source data
Writing destination data
Waiting for DMA request to clear
Writing channel controller data
Stalled
Done
Peripheral scatter-gather transition
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
EN
0
R
When this bit is 1, the DMA is enabled.
DMA Enable Status
8.7.2 DMA_CONFIG - DMA Configuration Register
Offset
0x004
Reset
Access
Bit Position
Name
Bit
Name
31:6
Reserved
Reset
Access Description
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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