EFM32WG Datasheet, PDF (39/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

7.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x018
0x01C
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x050
0x054
Name
MSC_CTRL
MSC_READCTRL
MSC_WRITECTRL
MSC_WRITECMD
MSC_ADDRB
MSC_WDATA
MSC_STATUS
MSC_IF
MSC_IFS
MSC_IFC
MSC_IEN
MSC_LOCK
MSC_CMD
MSC_CACHEHITS
MSC_CACHEMISSES
MSC_TIMEBASE
MSC_MASSLOCK
Type
RW
RW
RW
W1
RW
RW
R
R
W1
W1
RW
RW
W1
R
R
RW
RW
Description
Memory System Control Register
Read Control Register
Write Control Register
Write Command Register
Page Erase/Write Address Buffer
Write Data Register
Status Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
Configuration Lock Register
Command Register
Cache Hits Performance Counter
Cache Misses Performance Counter
Flash Write and Erase Timebase
Mass Erase Lock Register
7.5 Register Description
7.5.1 MSC_CTRL - Memory System Control Register
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31:1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
BUSFAULT
1
RW
Bus Fault Response Enable
When this bit is set, the memory system generates bus error response.
Value
0
1
Mode
GENERATE
IGNORE
Description
A bus fault is generated on access to unmapped code and system space.
Accesses to unmapped address space is ignored.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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