EFM32WG Datasheet, PDF (176/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Figure 14.2. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation
RDSETUP
(0, 1, 2, ...)
RDSTRB
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
EBI_AD[ 15:8]
ADDR[ 7:0]
Z
EBI_AD[ 7:0]
EBI_CSn
Z
DATA[ 7:0]
Z
EBI_REn
Figure 14.3. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation
WRSETUP
(0, 1, 2, ...)
WRSTRB
(1, 2, 3, ...)
WRHOLD
(0, 1, 2, ...)
EBI_AD[ 15:8]
ADDR[ 7:0]
Z
EBI_AD[ 7:0]
DATA[ 7:0]
Z
EBI_CSn
EBI_WEn
14.3.2 Multiplexed 16-bit Data, 16-bit Address Mode
In this mode, 16-bit address and 16-bit data is supported, but the utilization of an external latch is
required. The 16-bit address and 16-bit data bits are multiplexed on the EBI_AD lines. An illustration of
such a setup is shown in Figure 14.4 (p. 176) . This mode is set by programming the MODE field in
the EBI_CTRL register to D16A16ALE.
Note
In this mode the 16-bit address is organized in 2-byte chunks at memory addresses aligned
to 2-byte offsets. Consequently, the LSB of the 16-bit address will always be 0. In order to
double the address space, the 16-bit address is internally shifted one bit to the right so that
the LSB of the address driven into the EBI_AD bus, i.e. the EBI_AD[0]-bit, corresponds to
the second least significant bit of the address, i.e. ADDR[1]. At the external device, the LSB
of the address must be tied either low or high in order to create a full address.
Figure 14.4. EBI Address Latch Setup
EBI_AD
Lat ch ^ADDR
EBI
( EFM3 2 )
Ext ernal
ALE
Asy n c.
Device
DATA
Cont rol
At the start of the transaction the address is output on the EBI_AD lines. The Latch is controlled by the
ALE (Address Latch Enable) signal and stores the address. Then the data is read or written according
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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