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14.3.5 Page Mode Read Operation
Page mode read operation can enhance the performance of a sequence of consecutive asynchronous
read transactions by allowing data at subsequent intrapage addresses to be read faster. Page mode
operation is enabled by setting the PAGEMODE bitfield in the EBI_RDTIMING (or EBI_RDTIMINGn)
register to 1. If enabled, the RDPA bitfield in the EBI_PAGECTRL register defines the duration of an
intrapage access and the PAGELEN bitfield in the EBI_PAGECTRL register defines the number of
members in a page. Page mode reads can for example be triggered by consecutive reads resulting from
wide AHB reads which are automatically translated into multiple narrow external device reads. Page
mode reads can also be triggered by sequential reads resulting from the EBI prefetch unit.
The number of members in a page together with the width of the external device and the INCHIT bit of
the EBI_PAGECTRL register define whether an address change results in an interpage access or in an
intrapage access as shown in Table 14.1 (p. 179) .
Table 14.1. EBI Intrapage hit condition for read on address Addr (non-mentioned Addr bits are
unchanged)
PAGELEN, INCHIT
PAGELEN=MEMBER4, INCHIT=0
PAGELEN=MEMBER8, INCHIT=0
PAGELEN=MEMBER16, INCHIT=0
PAGELEN=MEMBER32, INCHIT=0
PAGELEN=MEMBER4, INCHIT=1
PAGELEN=MEMBER8, INCHIT=1
PAGELEN=MEMBER16, INCHIT=1
PAGELEN=MEMBER32, INCHIT=1
8-bit External Device
Addr[1:0] changed
Addr[2:0] changed
Addr[3:0] changed
Addr[4:0] changed
Addr[1:0] incremented by 1
Addr[2:0] incremented by 1
Addr[3:0] incremented by 1
Addr[4:0] incremented by 1
16-bit External Device
Addr[2:0] changed
Addr[3:0] changed
Addr[4:0] changed
Addr[5:0] changed
Addr[2:0] incremented by 2
Addr[3:0] incremented by 2
Addr[4:0] incremented by 2
Addr[5:0] incremented by 2
The initial page mode transaction uses the read setup and read strobe timing as shown in Figure 14.2 (p.
176) , Figure 14.5 (p. 177), Figure 14.7 (p. 177) or Figure 14.9 (p. 178) depending on the
used addressing mode. Subsequent transactions are started by changing the low-order address bits
and use the page access time defined in the RDPA bitfield of the EBI_PAGECTRL register. The read
hold state RDHOLD is only performed at the end of a page mode read sequence or when bus turn-
around occurs. Note that bus turn-around can occur even if only read transactions are performed as
the D16A16ALE addressing mode will drive the EBI_AD lines when programming the external address
latch. In this case one bus turn-around RDHOLDX cycle is automatically inserted in between the read
and the write action on the EBI_AD lines. Note that for the D16A16ALE addressing mode the RDPA
state immediately follows the ADDRSETUP state, so the HALFALE feature will typically be required to
satisfy the external address latch hold requirement. In the D8A24ALE addressing mode there is no need
to reprogram the external address latch for intrapage addresses as the external latch then only latches
the most significant, non-changed address lines. The following figures show typical page mode read
sequences for all addressing modes.
Figure 14.11. EBI Page Mode Read Operation for D8A8 addressing mode
EBI_AD[ 15:8]
EBI_AD[ 7:0]
EBI_CSn
EBI_REn
RDSETUP
(0, 1, 2, ...)
ADDR0
Z
RDSTRB
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDPA
(1, 2, 3, ...)
RDHOLD
(0, 1, 2, ...)
ADDR1
ADDR2
ADDR3
Z
DATA0
DATA1
DATA2
DATA3
Z
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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