EFM32WG Datasheet, PDF (286/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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1. When a SETUP packet is received, the core writes the received data to the receive FIFO, without
checking for available space in the receive FIFO and irrespective of the endpoint’s NAK and Stall
bit settings.
• The core internally sets the IN NAK and OUT NAK bits for the control IN/OUT endpoints on which
the SETUP packet was received.
2. For every SETUP packet received on the USB, 3 DWORDs of data is written to the receive FIFO,
and the SUPCNT field is decremented by 1.
• The first DWORD contains control information used internally by the core
• The second DWORD contains the first 4 bytes of the SETUP command
• The third DWORD contains the last 4 bytes of the SETUP command
3. When the Setup stage changes to a Data IN/OUT stage, the core writes an entry (Setup Stage Done
DWORD) to the receive FIFO, indicating the completion of the Setup stage.
4. On the AHB side, SETUP packets are emptied either by the DMA or the application. In DMA
mode, the SETUP packets (2 DWORDs) are written to the memory location programmed in the
USB_DOEPx_DMAADDR register, only if the endpoint is enabled. If the endpoint is not enabled, the
data remains in the receive FIFO until the enable bit is set.
5. When either the DMA or the application pops the Setup Stage Done DWORD from the receive FIFO,
the core interrupts the application with a USB_DOEPx_INT.SETUP interrupt, indicating it can process
the received SETUP packet.
• The core clears the endpoint enable bit for control OUT endpoints.
Application Programming Sequence
1. Program the USB_DOEPx_TSIZ register.
• USB_DOEPx_TSIZ.SUPCNT = 3
2. In DMA mode, program the USB_DOEPx_DMAADDR register and USB_DOEPx_CTL register with
the endpoint characteristics and set the Endpoint Enable bit (USB_DOEPx_CTL.EPENA).
• Endpoint Enable = 1
3. In Slave mode, wait for the USB_GINTSTS.RXFLVL interrupt and empty the data packets from the
receive FIFO, as explained in Packet Read from FIFO in Slave Mode (p. 290) . This step can be
repeated many times.
4. Assertion of the USB_DOEPx_INT.SETUP interrupt marks a successful completion of the SETUP
Data Transfer.
• On this interrupt, the application must read the USB_DOEPx_TSIZ register to determine the number
of SETUP packets received and process the last received SETUP packet.
• In DMA mode, the application must also determine if the interrupt bit
USB_DOEPx_INT.BACK2BACKSETUP is set. This bit is set if the core has received more
than three back-to-back SETUP packets. If this is the case, the application must ignore the
USB_DOEPx_TSIZ.SUPCNT value and use the USB_DOEPx_DMAADDR directly to read out the
last SETUP packet received. USB_DOEPx_DMAADDR-8 provides the pointer to the last valid
SETUP data.
Note
If the application has not enabled EP0 before the host sends the SETUP packet, the core
ACKs the SETUP packet and stores it in the FIFO, but does not write to the memory until
EP0 is enabled. When the application enables the EP0 (first enable) and clears the NAK
bit at the same time the Host sends DATA OUT, the DATA OUT is stored in the RxFIFO.
The OTG core then writes the setup data to the memory and disables the endpoint. Though
the application expects a Transfer Complete interrupt for the Data OUT phase, this does
not occur, because the SETUP packet, rather than the DATA OUT packet, enables EP0 the
first time. Thus, the DATA OUT packet is still in the RxFIFO until the application re-enables
EP0. The application must enable EP0 one more time for the core to process the DATA
OUT packet.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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