EFM32WG Datasheet, PDF (167/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

13.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x010
...
0x03C
Name
PRS_SWPULSE
PRS_SWLEVEL
PRS_ROUTE
PRS_CH0_CTRL
PRS_CHx_CTRL
PRS_CH11_CTRL
Type
W1
RW
RW
RW
RW
RW
Description
Software Pulse Register
Software Level Register
I/O Routing Register
Channel Control Register
Channel Control Register
Channel Control Register
13.5 Register Description
13.5.1 PRS_SWPULSE - Software Pulse Register
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31:12
11
10
9
8
7
6
5
4
3
2
Name
Reserved
CH11PULSE
See bit 0.
CH10PULSE
See bit 0.
CH9PULSE
See bit 0.
CH8PULSE
See bit 0.
CH7PULSE
See bit 0.
CH6PULSE
See bit 0.
CH5PULSE
See bit 0.
CH4PULSE
See bit 0.
CH3PULSE
See bit 0.
CH2PULSE
See bit 0.
Reset
Access Description
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
W1
Channel 11 Pulse Generation
0
W1
Channel 10 Pulse Generation
0
W1
Channel 9 Pulse Generation
0
W1
Channel 8 Pulse Generation
0
W1
Channel 7 Pulse Generation
0
W1
Channel 6 Pulse Generation
0
W1
Channel 5 Pulse Generation
0
W1
Channel 4 Pulse Generation
0
W1
Channel 3 Pulse Generation
0
W1
Channel 2 Pulse Generation
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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