EFM32WG Datasheet, PDF (227/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
23:22
21:20
19:17
16
15:13
12
11:10
9
8
7:5
4:2
Name
Reset
Access Description
Value
0
1
Mode
RGB565
RGB555
Description
RGB data is 565.
RGB data is 555.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
BANKSEL
0x0
RW
Graphics Bank
This field sets the Memory Bank containing the Frame Buffer
Value
0
1
2
3
Mode
BANK0
BANK1
BANK2
BANK3
Description
Memory bank 0 is used for Direct Drive, Masking, and Alpha Blending.
Memory bank 1 is used for Direct Drive, Masking, and Alpha Blending.
Memory bank 2 is used for Direct Drive, Masking, and Alpha Blending.
Memory bank 3 is used for Direct Drive, Masking, and Alpha Blending.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
WIDTH
0
This field sets TFT tranaction width.
RW
TFT Transaction Width
Value
0
1
Mode
BYTE
HALFWORD
Description
TFT Data is 8 bit wide.
TFT Data is 16 bit wide.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
COLOR1SRC
0
RW
This field sets the Masking/Alpha Blending Color1 Source.
Masking/Alpha Blending Color1 Source
Value
0
1
Mode
MEM
PIXEL1
Description
Masking/Alpha Blending color 1 is read from external memory.
Masking/Alpha Blending color 1 is read from EBI_TFTPIXEL1.
INTERLEAVE
0x0
RW
This field sets the TFT Direct Drive Interleave mode.
Interleave Mode
Value
0
1
2
Mode
UNLIMITED
ONEPERDCLK
PORCH
Description
Allow unlimited interleaved EBI accesses per EBI_DCLK period. This can cause jitter
on the EBI_DCLK
Allow 1 interleaved EBI access per EBI_DCLK period.
Only allow EBI accesses during TFT porches.
FBCTRIG
0
RW
TFT Frame Base Copy Trigger
Sets the trigger on which the TFTFRAMEBASE is copied into an internal buffer. Direct Drive address generation is based on the
internal buffer.
Value
0
1
Mode
VSYNC
HSYNC
Description
TFTFRAMEBASE is buffered on the vertical synchronization event EBI_VSYNC.
TFTFRAMEBASE is buffered on the horizontal synchronization event EBI_HSYNC.
SHIFTDCLKEN
0
RW
TFT EBI_DCLK Shift Enable
When this bit is set, EBI_DCLK edges are driven off the negative (instead of the positive) edge of the internal clock. SHIFTDCLKEN
is only allowed to be set to 1 if TFTHOLD in EBI_TFTTIMING is at least 1.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
MASKBLEND
0x0
RW
TFT Mask and Blend Mode
This field sets the Mask and Blend Mode.
Value
0
1
2
3
5
6
Mode
DISABLED
IMASK
IALPHA
IMASKIALPHA
EMASK
EALPHA
Description
Masking and Blending are disabled.
Internal Masking is enabled.
Internal Alpha Blending is enabled.
Internal Masking and Alpha Blending are enabled.
External Masking is enabled.
External Alpha Blending is enabled.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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