EFM32WG Datasheet, PDF (505/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

19.4 Register Map
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The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x054
0x0AC
Name
LEUARTn_CTRL
LEUARTn_CMD
LEUARTn_STATUS
LEUARTn_CLKDIV
LEUARTn_STARTFRAME
LEUARTn_SIGFRAME
LEUARTn_RXDATAX
LEUARTn_RXDATA
LEUARTn_RXDATAXP
LEUARTn_TXDATAX
LEUARTn_TXDATA
LEUARTn_IF
LEUARTn_IFS
LEUARTn_IFC
LEUARTn_IEN
LEUARTn_PULSECTRL
LEUARTn_FREEZE
LEUARTn_SYNCBUSY
LEUARTn_ROUTE
LEUARTn_INPUT
Type
RW
W1
R
RW
RW
RW
R
R
R
W
W
R
W1
W1
RW
RW
RW
R
RW
RW
Description
Control Register
Command Register
Status Register
Clock Control Register
Start Frame Register
Signal Frame Register
Receive Buffer Data Extended Register
Receive Buffer Data Register
Receive Buffer Data Extended Peek Register
Transmit Buffer Data Extended Register
Transmit Buffer Data Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
Pulse Control Register
Freeze Register
Synchronization Busy Register
I/O Routing Register
LEUART Input Register
19.5 Register Description
19.5.1 LEUARTn_CTRL - Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x000
Reset
Access
Bit Position
Name
Bit
31:16
15:14
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
TXDELAY
0x0
RW
TX Delay Transmission
Configurable delay before new transfers. Frames sent back-to-back are not delayed.
Value
0
1
2
Mode
NONE
SINGLE
DOUBLE
Description
Frames are transmitted immediately
Transmission of new frames are delayed by a single baud period
Transmission of new frames are delayed by two baud periods
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
505
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