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Table 28.2. ADC Differential Conversion
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Input/Reference
0.5
0.25
1/2048
0
-1/2048
-0.25
-0.5
Binary
011111111111
001111111111
000000000001
000000000000
111111111111
101111111111
100000000000
Results
7FF
3FF
001
000
FFF
BFF
800
Hex value
28.3.7.6 Resolution
The ADC gives out 12-bit results, by default. However, if full 12-bit resolution is not needed, it is possible
to speed up the conversion by selecting a lower resolution (N = 6 or 8 bits). For more information on the
accuracy of the ADC, the reader is referred to the electrical characteristics section for the device.
28.3.7.7 Oversampling
To achieve higher accuracy, hardware oversampling can be enabled individually for each mode (Set RES
in ADCn_SINGLECTRL/ADCn_SCANCTRL to 0x3). The oversampling rate (OVSRSEL in ADCn_CTRL)
can be set to any integer power of 2 from 2 to 4096 and the configuration is shared between the scan
and single sample mode (OVSRSEL field in ADCn_CTRL).
With oversampling, each selected input is sampled a number (given by the OVSR) of times, and the
results are filtered by a first order accumulate and dump filter to form the end result. The data presented in
the ADCn_SINGLEDATA and ADCn_SCANDATA registers are the direct contents of the accumulation
register (sum of samples). However, if the oversampling ratio is set higher than 16x, the accumulated
results are shifted to fit the MSB in bit 15 as shown in Table 28.3 (p. 688) .
Table 28.3. Oversampling Result Shifting and Resolution
Oversampling setting
2x
4x
8x
16x
32x
64x
128x
256x
512x
1024x
2048x
4096x
# right shifts
0
0
0
0
1
2
3
4
5
6
7
8
Result Resolution # bits
13
14
15
16
16
16
16
16
16
16
16
16
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
688
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