EFM32WG Datasheet, PDF (248/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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• Early Suspend
• USB Suspend
3. Wait for the USB_GINTSTS.USBRST interrupt, which indicates a reset has been detected on the
USB and lasts for about 10 ms. On receiving this interrupt, the application must perform the steps
listed in Initialization on USB Reset (p. 281)
4. Wait for the USB_GINTSTS.ENUMDONE interrupt. This interrupt indicates the end of reset on the
USB. On receiving this interrupt, the application must read the USB_DSTS register to determine the
enumeration speed and perform the steps listed in Initialization on Enumeration Completion (p. 281)
At this point, the device is ready to accept SOF packets and perform control transfers on control endpoint
0.
15.4.1.2.1 Device Connection
The device connect process varies depending on the if the VBUS is on or off when the device is
connected to the USB cable.
When VBUS is on When the Device is Connected
If VBUS is on when the device is connected to the USB cable, there is no SRP from the device. The
device connection flow is as follows:
1. The device triggers the USB_GINTSTS.SESSREQINT [bit 30] interrupt bit.
2. When the device application detects the USB_GINTSTS.SESSREQINT interrupt, it programs the
required bits in the USB_DCFG register.
3. When the Host drives Reset, the Device triggers USB_GINTSTS.USBRST [bit 12] on detecting the
Reset. The host then follows the USB 2.0 Enumeration sequence.
When VBUS is off When the Device is Connected
If VBUS is off when the device is connected to the USB cable, the device initiates SRP in OTG Revision
1.3 mode. The device connection flow is as follows:
1. The application initiates SRP by writing the Session Request bit in the OTG Control and Status
register. The core perform data-line pulsing followed by VBUS pulsing.
2. The host starts a new session by turning on VBUS, indicating SRP success. The core interrupts the
application by setting the Session Request Success Status Change bit in the OTG Interrupt Status
register.
3. The application reads the Session Request Success bit in the OTG Control and Status register and
programs the required bits in USB_DCFG register.
4. When Host drives Reset, the Device triggers USB_GINTSTS.USBRST on detecting the Reset. The
host then follows the USB 2.0 Enumeration sequence.
15.4.1.2.2 Device Disconnection
The device session ends when the USB cable is disconnected or if the VBUS is switched off by the Host.
The device disconnect flow is as follows:
1. When the USB cable is unplugged or when the VBUS is switched off by the Host, the Device core
trigger USB_GINTSTS.OTGINT [bit 2] interrupt bit.
2. When the device application detects USB_GINTSTS.OTGINT interrupt, it checks that the
USB_GOTGINT.SESENDDET (Session End Detected) bit is set to 1.
15.4.1.2.3 Device Soft Disconnection
The application can perform a soft disconnect by setting the Soft disconnect bit (SFTDISCON) in Device
Control Register (USB_DCTL).
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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