EFM32WG Datasheet, PDF (373/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
31:14
13:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
HAINT
0x0000
R
Channel Interrupt for channel 0 - 13.
When the interrupt bit for a channel x set, one or more of the interrupt flags in the USB_HCx_INT are set.
15.6.33 USB_HAINTMSK - Host All Channels Interrupt Mask Register
The Host All Channel Interrupt Mask register works with the Host All Channel Interrupt register to interrupt
the application when an event occurs on a channel. There is one interrupt mask bit per channel. Set
bits to unmask.
Offset
0x3C418
Bit Position
Reset
Access
Name
Bit
31:14
13:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
HAINTMSK
0x0000
RW
Channel Interrupt Mask for channel 0 - 13
Set bit n to unmask channel n interrupts.
15.6.34 USB_HPRT - Host Port Control and Status Register
This register is available only in Host mode. This register holds USB port-related information such as USB
reset, enable, suspend, resume, connect status, and test mode for the port. Some bits in this register
can trigger an interrupt to the application through the Host Port Interrupt bit of the Core Interrupt register
(USB_GINTSTS.PRTINT). On a Port Interrupt, the application must read this register and clear the bit
that caused the interrupt. For the RW1 bits, the application must write a 1 to the bit to clear the interrupt.
Offset
0x3C440
Reset
Bit Position
Access
Name
Bit
31:19
18:17
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
PRTSPD
0x0
R
Port Speed
Indicates the speed of the device attached to this port.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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