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a. The core receives a corrupted isochronous IN token on at least one isochronous IN endpoint. In
this case, the application detects a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN
Transfer) interrupt.
b. The application or DMA is slow to write the complete data payload to the transmit FIFO
and an IN token is received before the complete data payload is written to the FIFO. In this
case, the application detects a USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When
TxFIFO Empty) interrupt. The application can ignore this interrupt, as it eventually results in
a USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt at the end of
periodic frame.
i. The core transmits a zero-length data packet on the USB in response to the received IN token.
2. In either of the aforementioned cases, in Slave mode, the application must stop writing the data
payload to the transmit FIFO as soon as possible.
3. The application must set the NAK bit and the disable bit for the endpoint. In DMA mode, the core
automatically stops fetching the data payload when the endpoint disable bit is set.
4. The core disables the endpoint, clears the disable bit, and asserts the Endpoint Disable interrupt for
the endpoint.
Application Programming Sequence
1. The application can ignore the USB_DIEPx_INT.INTKNTXFEMP (IN Token Received When
TxFIFO empty) interrupt on any isochronous IN endpoint, as it eventually results in a
USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt.
2. Assertion of the USB_GINTSTS.INCOMPISOIN (Incomplete Isochronous IN Transfer) interrupt
indicates an incomplete isochronous IN transfer on at least one of the isochronous IN endpoints.
3. The application must read the Endpoint Control register for all isochronous IN endpoints to detect
endpoints with incomplete IN data transfers.
4. In Slave mode, the application must stop writing data to the Periodic Transmit FIFOs associated with
these endpoints on the AHB.
5. In both modes of operation, program the following fields in the USB_DIEPx_CTL register to disable
the endpoint.
• USB_DIEPx_CTL.SNAK = 1
• USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1
6. The USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt’s assertion indicates that the core has
disabled the endpoint.
• At this point, the application must flush the data in the associated transmit FIFO or overwrite the
existing data in the FIFO by enabling the endpoint for a new transfer in the next frame. To flush the
data, the application must use the USB_GRSTCTL register.
15.4.4.2.3.7 Stalling Non-Isochronous IN Endpoints
This section describes how the application can stall a non-isochronous endpoint.
Application Programming Sequence
1. Disable the IN endpoint to be stalled. Set the Stall bit as well.
2. USB_DIEPx_CTL.EPDIS (Endpoint Disable) = 1, when the endpoint is already enabled
• USB_DIEPx_CTL.STALL = 1
• The Stall bit always takes precedence over the NAK bit
3. Assertion of the USB_DIEPx_INT.EPDISBLD (Endpoint Disabled) interrupt indicates to the
application that the core has disabled the specified endpoint.
4. The application must flush the Non-periodic or Periodic Transmit FIFO, depending on the endpoint
type. In case of a non-periodic endpoint, the application must re-enable the other non-periodic
endpoints, which do not need to be stalled, to transmit data.
5. Whenever the application is ready to end the STALL handshake for the endpoint, the
USB_DIEPx_CTL.STALL bit must be cleared.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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