EFM32WG Datasheet, PDF (708/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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table. The sine signal is controlled by the PRS line selected by CH0PRSSEL in DACn_CH0CTRL. When
the PRS line is low, a voltage of Vref/2 will be produced. When the line is high, a sine wave will be
produced. Each period, starting at 0 degrees, is made up of 16 samples and the frequency is given by
Equation 29.4 (p. 708) :
DAC Sine Generation
f_sine = f_HFPERCLK / 32 x (PRESC + 1)
(29.4)
The SINE wave will be output on channel 0. If DIFF is set in DACn_CTRL, the sine wave will be output
on both channels (if enabled), but inverted (see Figure 29.1 (p. 705) ). Note that when OUTENPRS
in DACn_CTRL is set, the sine output will be reset to 0 degrees when the PRS line selected by
CH1PRSSEL is low.
Figure 29.3. DAC Sine Mode
CH0 PRS
CH1 PRS
D ACn _OUT1
D ACn _OUT0
Hi-Z
Hi-Z
Vref
Vref/2
0
Vref
Vref/2
0
29.3.6 Interrupts and PRS Output
Both DAC channels have separate interrupt flags (in DACn_IF) indicating that a conversion has finished
on the channel and that new data can be written to the data registers. Setting one of these flags will result
in a DAC interrupt if the corresponding interrupt enable bit is set in DACn_IEN. All generated interrupts
from the DAC will activate the same interrupt vector when enabled.
The DAC has two PRS outputs which will carry a one cycle (HFPERCLK) high pulse when the
corresponding channel has finished a conversion.
29.3.7 DMA Request
The DAC sends out a DMA request when a conversion on a channel is complete. This request is cleared
when the corresponding channel’s data register is written.
29.3.8 Analog Output
Each DAC channel has its own output pin (DACn_OUT0 and DACn_OUT1) in addition to an internal
loopback to the ADC and ACMP. These outputs can be enabled and disabled individually in the EN
field in DACn_CHxCTRL registers in combination with OUTPUTSEL in DACn_CTRL. The DAC outputs
can also be directed to the ADC and ACMP, which is also configurable in the OUTPUTSEL field in
DACn_CTRL.
The DAC outputs are tri-stated when the channels are not enabled. By setting the OUTENPRS
bit in DACn_CTRL, the outputs are also tri-stated when the PRS line selected by CH1PRSSEL in
DACn_CH1CTRL is low. When the PRS signal is high, the outputs are enabled as normal.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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