EFM32WG Datasheet, PDF (72/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

8.6 Register Map
...the world's most energy friendly microcontrollers
The offset register address is relative to the registers base address.
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x04C
0xE10
0xE18
0x1000
0x1004
0x1008
0x100C
0x1010
0x1014
0x1020
0x1024
0x1060
0x1100
...
0x112C
Name
DMA_STATUS
DMA_CONFIG
DMA_CTRLBASE
DMA_ALTCTRLBASE
DMA_CHWAITSTATUS
DMA_CHSWREQ
DMA_CHUSEBURSTS
DMA_CHUSEBURSTC
DMA_CHREQMASKS
DMA_CHREQMASKC
DMA_CHENS
DMA_CHENC
DMA_CHALTS
DMA_CHALTC
DMA_CHPRIS
DMA_CHPRIC
DMA_ERRORC
DMA_CHREQSTATUS
DMA_CHSREQSTATUS
DMA_IF
DMA_IFS
DMA_IFC
DMA_IEN
DMA_CTRL
DMA_RDS
DMA_LOOP0
DMA_LOOP1
DMA_RECT0
DMA_CH0_CTRL
DMA_CHx_CTRL
DMA_CH11_CTRL
Type
R
W
RW
R
R
W1
RW1
W1
RW1
W1
RW1
W1
RW1
W1
RW1
W1
RW
R
R
R
W1
W1
RW
RW
RW
RWH
RW
RWH
RW
RW
RW
Description
DMA Status Registers
DMA Configuration Register
Channel Control Data Base Pointer Register
Channel Alternate Control Data Base Pointer Register
Channel Wait on Request Status Register
Channel Software Request Register
Channel Useburst Set Register
Channel Useburst Clear Register
Channel Request Mask Set Register
Channel Request Mask Clear Register
Channel Enable Set Register
Channel Enable Clear Register
Channel Alternate Set Register
Channel Alternate Clear Register
Channel Priority Set Register
Channel Priority Clear Register
Bus Error Clear Register
Channel Request Status
Channel Single Request Status
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable register
DMA Control Register
DMA Retain Descriptor State
Channel 0 Loop Register
Channel 1 Loop Register
Channel 0 Rectangle Register
Channel Control Register
Channel Control Register
Channel Control Register
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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