EFM32WG Datasheet, PDF (638/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Value
3
4
5
6
7
8
9
10
11
Reset
Mode
PRSCH3
PRSCH4
PRSCH5
PRSCH6
PRSCH7
PRSCH8
PRSCH9
PRSCH10
PRSCH11
Access Description
Description
PRS Channel 3 selected as input
PRS Channel 4 selected as input
PRS Channel 5 selected as input
PRS Channel 6 selected as input
PRS Channel 7 selected as input
PRS Channel 8 selected as input
PRS Channel 9 selected as input
PRS Channel 10 selected as input
PRS Channel 11 selected as input
9
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
8
INPUT
0
RW
Select input to the LESENSE decoder
Value
0
1
Mode
SENSORSTATE
PRS
Description
The SENSORSTATE register is used as input to the decoder.
PRS channels are used as input to the decoder.
7
PRSCNT
0
RW
Enable count mode on decoder PRS channels 0 and 1
When set, decoder PRS0 and PRS1 will be used to produce output which can be used by a PCNT to count up or down.
6
HYSTIRQ
0
RW
Enable decoder hysteresis on interrupt requests
When set, hysteresis is enabled in the decoder, suppressing interrupt requests.
5
HYSTPRS2
0
RW
Enable decoder hysteresis on PRS2 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 2
4
HYSTPRS1
0
RW
Enable decoder hysteresis on PRS1 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 1
3
HYSTPRS0
0
RW
Enable decoder hysteresis on PRS0 output
When set, hysteresis is enabled in the decoder, suppressing changes on PRS channel 0
2
INTMAP
0
RW
Enable decoder to channel interrupt mapping
When set, a transition from state x in the decoder will set interrupt flag CHx
1
ERRCHK
0
RW
Enable check of current state
When set, the decoder checks the current state in addition to the states defined in TCONF
0
DISABLE
0
RW
Disable the decoder
When set, the decoder is disabled. When disabled the decoder will keep its current state
25.5.5 LESENSE_BIASCTRL - Bias Control Register (Async Reg)
For more information about Asynchronous Registers please see Section 5.3 (p. 21) .
Offset
0x010
Reset
Access
Bit Position
Name
Bit
Name
31:2
Reserved
Reset
Access Description
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
638
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