EFM32WG Datasheet, PDF (81/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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8.7.11 DMA_CHENS - Channel Enable Set Register
Offset
0x028
Reset
Bit Position
Access
Name
Bit
31:12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CH11ENS
0
RW1
Channel 11 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH10ENS
0
RW1
Channel 10 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH9ENS
0
RW1
Channel 9 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH8ENS
0
RW1
Channel 8 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH7ENS
0
RW1
Channel 7 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH6ENS
0
RW1
Channel 6 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH5ENS
0
RW1
Channel 5 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH4ENS
0
RW1
Channel 4 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH3ENS
0
RW1
Channel 3 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH2ENS
0
RW1
Channel 2 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH1ENS
0
RW1
Channel 1 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
CH0ENS
0
RW1
Channel 0 Enable Set
Write to 1 to enable this channel. Reading returns the enable status of the channel.
8.7.12 DMA_CHENC - Channel Enable Clear Register
Offset
0x02C
Reset
Access
Bit Position
Name
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
81
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