EFM32WG Datasheet, PDF (417/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Whenever arbitration is lost, the ARBLOST interrupt flag in I2Cn_IF is set, any lines held are released,
and the I²C device goes idle. If an I²C master loses arbitration during the transmission of an address,
another master may be trying to address it. The master therefore receives the rest of the address, and
if the address matches the slave address of the master, the master goes into either slave transmitter
or slave receiver mode.
Note
Arbitration can be lost both when operating as a master and when operating as a slave.
16.3.6 Buffers
16.3.6.1 Transmit Buffer and Shift Register
The I²C transmitter is double buffered through the transmit buffer and transmit shift register as shown in
Figure 16.1 (p. 412) . A byte is loaded into the transmit buffer by writing to I2Cn_TXDATA. When the
transmit shift register is empty and ready for new data, the byte from the transmit buffer is then loaded
into the shift register. The byte is then kept in the shift register until it is transmitted. When a byte has
been transmitted, a new byte is loaded into the shift register (if available in the transmit buffer). If the
transmit buffer is empty, then the shift register also remains empty. The TXC flag in I2Cn_STATUS and
the TXC interrupt flags in I2Cn_IF are then set, signaling that the transmit shift register is out of data. TXC
is cleared when new data becomes available, but the TXC interrupt flag must be cleared by software.
Whenever a byte is loaded from the transmit buffer to the transmit shift register, the TXBL flag in
I2Cn_STATUS and the TXBL interrupt flag in I2Cn_IF are set. This indicates that there is room in the
buffer for more data. TXBL is cleared automatically when data is written to the buffer.
If a write is attempted to the transmit buffer while it is not empty, the TXOF interrupt flag in I2Cn_IF is set,
indicating the overflow. The data already in the buffer remains preserved, and no new data is written.
The transmit buffer and the transmit shift register can be cleared by setting command bit CLEARTX in
I2Cn_CMD. This will prevent the I²C module from transmitting the data in the buffer and the shift register,
and will make them available for new data. Any byte currently being transmitted will not be aborted.
Transmission of this byte will be completed.
16.3.6.2 Receive Buffer and Shift Register
Like the transmitter, the I²C receiver is double buffered. The receiver uses the receive buffer and receive
shift register as shown in Figure 16.1 (p. 412) . When a byte has been fully received by the receive
shift register, it is loaded into the receive buffer if there is room for it. Otherwise, the byte waits in the
shift register until space becomes available in the buffer.
When a byte becomes available in the receive buffer, the RXDATAV in I2Cn_STATUS and RXDATAV
interrupt flag in I2Cn_IF are set. The data can now be fetched from the buffer using I2Cn_RXDATA.
Reading from this register will pull a byte out of the buffer, making room for a new byte and clearing
RXDATAV in I2Cn_STATUS and RXDATAV in I2Cn_IF in the process.
If a read from the receive buffer is attempted through I2Cn_RXDATA while the buffer is empty, the RXUF
interrupt flag in I2Cn_IF is set, and the data read from the buffer is undefined.
I2Cn_RXDATAP can be used to read data from the receive buffer without removing it from the buffer.
The RXUF interrupt flag in I2Cn_IF will never be set as a result of reading from I2Cn_RXDATAP, but
the data read through I2Cn_RXDATAP when the receive buffer is empty is still undefined.
16.3.7 Master Operation
A bus transaction is initiated by transmitting a START condition (S) on the bus. This is done by setting
the START bit in I2Cn_CMD. The command schedules a START condition, and makes the I²C module
generate a start condition whenever the bus becomes free.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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