EFM32WG Datasheet, PDF (652/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Set to enable interrupt on the CH8 interrupt flag
7
CH7
0
RW
Set to enable interrupt on the CH7 interrupt flag
6
CH6
0
RW
Set to enable interrupt on the CH6 interrupt flag
5
CH5
0
RW
Set to enable interrupt on the CH5 interrupt flag
4
CH4
0
RW
Set to enable interrupt on the CH4 interrupt flag
3
CH3
0
RW
Set to enable interrupt on the CH3 interrupt flag
2
CH2
0
RW
Set to enable interrupt on the CH2 interrupt flag
1
CH1
0
RW
Set to enable interrupt on the CH1 interrupt flag
0
CH0
0
RW
Set to enable interrupt on the CH0 interrupt flag
25.5.21 LESENSE_SYNCBUSY - Synchronization Busy Register
Offset
0x050
Reset
Access
Bit Position
Name
Bit
31:27
26
25
24
23
22
21
20:18
17
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
EVAL
0
R
LESENSE_CHx_EVAL Register Busy
Set when the value written to LESENSE_CHx_EVAL is being synchronized.
INTERACT
0
R
LESENSE_CHx_INTERACT Register Busy
Set when the value written to LESENSE_CHx_INTERACT is being synchronized.
TIMING
0
R
LESENSE_CHx_TIMING Register Busy
Set when the value written to LESENSE_CHx_TIMING is being synchronized.
DATA
0
R
LESENSE_BUFx_DATA Register Busy
Set when the value written to LESENSE_BUFx_DATA is being synchronized.
TCONFB
0
R
LESENSE_STx_TCONFB Register Busy
Set when the value written to LESENSE_STx_TCONFB is being synchronized.
TCONFA
0
R
LESENSE_STx_TCONFA Register Busy
Set when the value written to LESENSE_STx_TCONFA is being synchronized.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
POWERDOWN
0
R
LESENSE_POWERDOWN Register Busy
Set when the value written to LESENSE_POWERDOWN is being synchronized.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
652
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