EFM32WG Datasheet, PDF (74/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
5
CHPROT
0
W
Channel Protection Control
Control whether accesses done by the DMA controller are privileged or not. When CHPROT = 1 then HPROT is HIGH and the access
is privileged. When CHPROT = 0 then HPROT is LOW and the access is non-privileged.
4:1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
EN
0
W
Enable DMA
Set this bit to enable the DMA controller.
8.7.3 DMA_CTRLBASE - Channel Control Data Base Pointer Register
Offset
0x008
Bit Position
Reset
Access
Name
Bit
Name
Reset
Access Description
31:0
CTRLBASE
0x00000000
RW
Channel Control Data Base Pointer
The base pointer for a location in system memory that holds the channel control data structure. This register must be written to point
to a location in system memory with the channel control data structure before the DMA can be used. Note that ctrl_base_ptr[8:0]
must be 0.
8.7.4 DMA_ALTCTRLBASE - Channel Alternate Control Data Base Pointer
Register
Offset
0x00C
Bit Position
Reset
Access
Name
Bit
Name
31:0
ALTCTRLBASE
Reset
0x00000100
Access
R
Description
Channel Alternate Control Data Base Pointer
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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