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33.3.7.2 Frame rate Division Register
The frame rate is set in the CMU by programming the frame rate division bits FDIV in CMU_LCDCTRL.
This setting should not be changed while the LCD driver is running. The equation for calculating the
resulting frame rate is given from Equation 33.1 (p. 791)
LCD Frame rate Calculation
LFACLK_LCD = LFACLK_LCDpre/(1 + FDIV)
(33.1)
Table 33.9. LCD Frame rate Conversion Table
MUX Mode
Frame- rate
formula
Static
Duplex
Triplex
Quadruplex
Sextaplex
Octaplex
LFACLK_LCD/2
LFACLK_LCD/4
LFACLK_LCD/6
LFACLK_LCD/8
LFACLK_LCD/12
LFACLK_LCD/16
LFACLK_LCDpre = 2
kHz
Min
Max
128
1024
64
512
43
341
32
256
21.33 170.67
16
128
Resulting Frame rate, CLK_FRAME(Hz)
LFACLK_LCDpre = 1 LFACLK_LCDpre =
kHz
0.5 kHz
Min
Max Min
Max
64
512
32
256
32
256
16
128
21
171
11
85
16
128
8
64
10.67 85.33 5.33
42.67
8
64
4
32
LFACLK_LCDpre =
0.25 kHz
Min
Max
16
128
8
64
5
43
4
32
2.67
21.33
2
16
Table settings: Min: FDIV = 7, Max: FDIV = 0
33.3.8 Data Update
The LCD Driver logic that controls the output waveforms is clocked on LFACLK_LCDpre. The LCD data and
Control Registers are clocked on the HFCORECLK. To avoid metastability and unpredictable behavior,
the data in the Segment Data (SEGDn) registers must be synchronized to the LCD driver logic. Also,
it is important that data is updated at the beginning of an LCD frame since the segment waveform
depends on the segment data and a change in the middle of a frame may lead to a DC-component in that
frame. The LCD driver has dedicated functionality to synchronize data transfer to the LCD frames. The
synchronization logic is applied to all data that need to be updated at the beginning of the LCD frames:
• LCD_SEGDn
• LCD_AREGA
• LCD_AREGB
• LCD_BACTRL
The different methods to update data are controlled by the UDCTRL bits in LCD_CTRL.
Table 33.10. LCD Update Data Control (UDCTRL) Bits
UDCTRL
00
01
Mode
REGULAR
FCEVENT
10
FRAMESTART
Description
The data transfer is controlled by SW and data synchronization is
initiated by writing data to the buffers. Data is transferred as soon as
possible, possibly creating a frame with a DC component on the LCD.
The data transfer is done at the next event triggered by the Frame
Counter (FC). See Section 33.3.10 (p. 792) for details on how to
configure the Frame Counter. Optionally, the Frame Counter can also
generate an interrupt at every event.
The data transfer is done at frame-start.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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