EFM32WG Datasheet, PDF (478/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
2
MASTER
0
R
SPI Master Mode
Set when the USART operates as a master. Set using the MASTEREN command and clear using the MASTERDIS command.
1
TXENS
0
R
Transmitter Enable Status
Set when the transmitter is enabled.
0
RXENS
0
R
Receiver Enable Status
Set when the receiver is enabled.
17.5.6 USARTn_CLKDIV - Clock Control Register
Offset
0x014
Bit Position
Reset
Access
Name
Bit
31:21
20:6
5:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
DIV
0x0000
RW
Fractional Clock Divider
Specifies the fractional clock divider for the USART.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
17.5.7 USARTn_RXDATAX - RX Buffer Data Extended Register
Offset
0x018
Reset
Access
Bit Position
Name
Bit
31:16
15
14
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
FERR
0
R
Data Framing Error
Set if data in buffer has a framing error. Can be the result of a break condition.
PERR
0
R
Data Parity Error
Set if data in buffer has a parity error (asynchronous mode only).
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
478
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