EFM32WG Datasheet, PDF (375/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
The core sets this bit when a device connection is detected to trigger an interrupt to the application using the Host Port Interrupt bit of
the Core Interrupt register (USB_GINTSTS.PRTINT). This bit can be set only by the core and the application should write 1 to clear
it. The application must write a 1 to this bit to clear the interrupt.
0
PRTCONNSTS
0
R
Port Connect Status
When this bit is 1 a device is attached to the port.
15.6.35 USB_HCx_CHAR - Host Channel x Characteristics Register
Offset
0x3C500
Bit Position
Reset
Access
Name
Bit
31
30
29
28:22
21:20
19:18
17
16
15
Name
Reset
Access Description
CHENA
0
RW1
Channel Enable
This field is set by the application and cleared by the core. The state of this bit reflects the channel enable status.
CHDIS
0
RW1
Channel Disable
The application sets this bit to stop transmitting/receiving data on a channel, even before the transfer for that channel is complete.
The application must wait for the Channel Disabled interrupt before treating the channel as disabled.
ODDFRM
0
RW
Odd Frame
This field is set (reset) by the application to indicate that the OTG host must perform a transfer in an odd frame. This field is applicable
for only periodic (isochronous and interrupt) transactions.
DEVADDR
0x00
RW
Device Address
This field selects the specific device serving as the data source or sink.
MC
0x0
RW
Multi Count
For periodic transfers this field indicates to the host the number of transactions that must be executed per frame for this periodic
endpoint. For non-periodic transfers, this field is used only in DMA mode, and specifies the number packets to be fetched for this
channel before the internal DMA engine changes arbitration.
EPTYPE
0x0
RW
Endpoint Type
Indicates the transfer type selected.
Value
0
1
2
3
Mode
CONTROL
ISO
BULK
INT
Description
Control endpoint.
Isochronous endpoint.
Bulk endpoint.
Interrupt endpoint.
LSPDDEV
0
RW
Low-Speed Device
This field is set by the application to indicate that this channel is communicating to a low-speed device.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
EPDIR
0
RW
Indicates whether the transaction is IN or OUT.
Endpoint Direction
Value
0
1
Mode
OUT
IN
Description
Direction is OUT.
Direction is IN.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
375
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