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USART Synchronous Mode Clock Division Factor
USARTn_CLKDIV = 256 x (f_HFPERCLK/(2 x brdesired) - 1)
(17.4)
When the USART operates in master mode, the highest possible bit rate is half the peripheral clock rate.
When operating in slave mode however, the highest bit rate is an eighth of the peripheral clock:
• Master mode: br_max = f_HFPERCLK/2
• Slave mode: br_max = f_HFPERCLK/8
On every clock edge data on the data lines, MOSI and MISO, is either set up or sampled. When CLKPHA
in USARTn_CTRL is cleared, data is sampled on the leading clock edge and set-up is done on the
trailing edge. If CLKPHA is set however, data is set-up on the leading clock edge, and sampled on the
trailing edge. In addition to this, the polarity of the clock signal can be changed by setting CLKPOL in
USARTn_CTRL, which also defines the idle state of the clock. This results in four different modes which
are summarized in Table 17.8 (p. 462) . Figure 17.15 (p. 462) shows the resulting timing of data
set-up and sampling relative to the bus clock.
Table 17.8. USART SPI Modes
SPI mode
0
1
2
3
CLKPOL
0
0
1
1
CLKPHA
0
1
0
1
Leading edge
Rising, sample
Rising, set-up
Falling, sample
Falling, set-up
Trailing edge
Falling, set-up
Falling, sample
Rising, set-up
Rising, sample
Figure 17.15. USART SPI Timing
CLKPOL = 0
USn _CLK
CLKPOL = 1
USn _CS
CLKPHA = 0 X
0
1
2
3
4
5
6
7
X
USn _TX/
USn _RX
CLKPHA = 1
X
0
1
2
3
4
5
6
7
X
If CPHA=1, the TX underflow flag, TXUF, will be set on the first setup clock edge of a frame in slave
mode if TX data is not available. If CPHA=0, TXUF is set if data is not available in the transmit buffer
three HFPERCLK cycles prior to the first sample clock edge. The RXDATAV flag is updated on the last
sample clock edge of a transfer, while the RX overflow interrupt flag, RXOF, is set on the first sample
clock edge if the receive buffer overflows. When a transfer has been performed, interrupt flags TXBL
and TXC are updated on the first setup clock edge of the succeeding frame, or when CS is deasserted.
17.3.3.3 Master Mode
When in master mode, the USART is in full control of the data flow on the synchronous bus. When
operating in full duplex mode, the slave cannot transmit data to the master without the master transmitting
to the slave. The master outputs the bus clock on USn_CLK.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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