EFM32WG Datasheet, PDF (293/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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4. If the application is setting or clearing a STALL for an endpoint due to a SetFeature.Endpoint Halt or
ClearFeature.Endpoint Halt command, the Stall bit must be set or cleared before the application sets
up the Status stage transfer on the control endpoint.
15.4.4.2.2.8 Generic Non-Isochronous OUT Data Transfers in DMA and Slave Modes
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the host, it must initialize an endpoint
as described in Endpoint Initialization (p. 281) . See Packet Read from FIFO in Slave Mode (p. 290) .
This section describes a regular non-isochronous OUT data transfer (control, bulk, or interrupt).
Application Requirements
1. Before setting up an OUT transfer, the application must allocate a buffer in the memory to
accommodate all data to be received as part of the OUT transfer, then program that buffer’s size and
start address (in DMA mode) in the endpoint-specific registers.
1. For OUT transfers, the Transfer Size field in the endpoint’s Transfer Size register must be a multiple
of the maximum packet size of the endpoint, adjusted to the DWORD boundary.
if (mps[epnum] mod 4) == 0
transfer size[epnum] = n * (mps[epnum]) //Dword Aligned
else
transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) //Non Dword Aligned
packet count[epnum] = n
n>0
2. In DMA mode, the core stores a received data packet in the memory, always starting on a DWORD
boundary. If the maximum packet size of the endpoint is not a multiple of 4, the core inserts byte pads
at end of a maximum-packet-size packet up to the end of the DWORD.
3. On any OUT endpoint interrupt, the application must read the endpoint’s Transfer Size register to
calculate the size of the payload in the memory. The received payload size can be less than the
programmed transfer size.
• Payload size in memory = application-programmed initial transfer size – core updated final transfer
size
• Number of USB packets in which this payload was received = application-programmed initial packet
count – core updated final packet count
Internal Data Flow
1. The application must set the Transfer Size and Packet Count fields in the endpoint-specific registers,
clear the NAK bit, and enable the endpoint to receive the data.
2. Once the NAK bit is cleared, the core starts receiving data and writes it to the receive FIFO, as long
as there is space in the receive FIFO. For every data packet received on the USB, the data packet
and its status are written to the receive FIFO. Every packet (maximum packet size or short packet)
written to the receive FIFO decrements the Packet Count field for that endpoint by 1.
• OUT data packets received with Bad Data CRC are flushed from the receive FIFO automatically.
• After sending an ACK for the packet on the USB, the core discards non-isochronous OUT data
packets that the host, which cannot detect the ACK, re-sends. The application does not detect
multiple back-to-back data OUT packets on the same endpoint with the same data PID. In this case
the packet count is not decremented.
• If there is no space in the receive FIFO, isochronous or non-isochronous data packets are ignored
and not written to the receive FIFO. Additionally, non-isochronous OUT tokens receive a NAK
handshake reply.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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