EFM32WG Datasheet, PDF (271/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 Frame)
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
The application is expected to write the requests for the same channel when the Request queue space
is available up to the count specified in the MC field before switching to another channel (if any).
15.4.3.6.11 Interrupt OUT Transactions in DMA Mode
To initialize the core after power-on reset, the application must follow the sequence in Overview:
Programming the Core (p. 246) . Before it can communicate with the connected device, it must initialize
a channel as described in Channel Initialization (p. 252) .
A typical interrupt OUT operation in DMA mode is shown in Figure 15.16 (p. 272) . See channel 1
(ch_1). The assumptions are:
• The application is attempting to transmit one packet in every frame (up to 1 maximum packet size
of 1,024 bytes).
• The Periodic Transmit FIFO can hold one packet (1 KB for FS).
• Periodic Request Queue depth = 4.
15.4.3.6.11.1 Normal Interrupt OUT Operation
1. Initialize and enable channel 1 as explained in Channel Initialization (p. 252) .
2. The host starts fetching the first packet as soon the channel is enabled and writes the OUT request
along with the last DWORD fetch. In high-bandwidth transfers, the host continues fetching the next
packet (up to the value specified in the MC field) before switching to the next channel.
3. The host attempts to send the OUT token in the beginning of the next odd frame.
4. After successfully transmitting the packet, the host generates a CHHLTD interrupt.
5. In response to the CHHLTD interrupt, reinitialize the channel for the next transfer.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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