EFM32WG Datasheet, PDF (370/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
15:12
11:0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
INEPNTXFSTADDR
0xE00
RW
IN Endpoint FIFO 6 Transmit RAM Start Address
This field contains the memory start address for IN endpoint Transmit FIFO 6.
15.6.28 USB_HCFG - Host Configuration Register
This register configures the core after power-on. Do not make changes to this register after initializing
the host.
Offset
0x3C400
Bit Position
Reset
Access
Name
Bit
31
30:16
15:8
7
6:3
2
1:0
Name
Reset
Access Description
MODECHTIMEN
0
RW
Mode Change Time
This bit is used to enable/disable the Host core to wait 200 clock cycles at the end of Resume before changing the PHY opmode to
normal operation. When set to 0 the Host core waits for either 200 PHY clock cycles or a linestate of SE0 at the end of resume to
the change the PHY opmode to normal operation. When set to 1 the Host core waits only for a linstate of SE0 at the end of resume
to change the PHY opmode to normal operation.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RESVALID
0x00
RW
Resume Validation Period
This field is effective only when USB_HCFG.ENA32KHZS is set. It will control the resume period when the core resumes from
suspend. The core counts for RESVALID number of clock cycles to detect a valid resume when USB_HCFG.ENA32KHZS is set.
ENA32KHZS
0
RW
Enable 32 KHz Suspend mode
When this bit is set the core expects that the clock to the core during Suspend is switched from 48 MHz to 32 KHz.
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
FSLSSUPP
0
RW
FS- and LS-Only Support
The application uses this bit to control the core's enumeration speed. Using this bit, the application can make the core enumerate as
a FS host, even If the connected device supports HS traffic. Do not make changes to this field after initial programming.
Value
0
1
Mode
HSFSLS
FSLS
Description
HS/FS/LS, based on the maximum speed supported by the connected device.
FS/LS-only, even If the connected device can support HS.
FSLSPCLKSEL
0x0
RW
FS/LS PHY Clock Select
Use this field to set the internal PHY clock frequency. Set to 48 MHz in FS Host mode and 6 MHz in LS Host mode. When you select
a 6 MHz clock during LS mode, you must do a soft reset.
Value
1
2
Mode
DIV1
DIV8
Description
Internal PHY clock is running at 48 MHz (undivided).
Internal PHY clock is running at 6 MHz (48 MHz divided by 8).
15.6.29 USB_HFIR - Host Frame Interval Register
This register stores the frame interval information for the current speed to which the core has
enumerated.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
370
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