EFM32WG Datasheet, PDF (825/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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List of Figures
3.1. Block Diagram of EFM32WG ................................................................................................................... 7
3.2. Energy Mode Indicator ............................................................................................................................. 7
4.1. Interrupt Operation ................................................................................................................................ 13
5.1. EFM32WG Bus System ......................................................................................................................... 16
5.2. System Address Space .......................................................................................................................... 16
5.3. Write operation to Low Energy Peripherals ................................................................................................ 22
5.4. Read operation from Low Energy Peripherals ............................................................................................. 23
6.1. AAP - Authentication Access Port ............................................................................................................ 27
6.2. Device Unlock ...................................................................................................................................... 28
6.3. AAP Expansion .................................................................................................................................... 28
7.1. Revision Number Extraction .................................................................................................................... 34
7.2. Instruction Cache .................................................................................................................................. 36
8.1. DMA Block Diagram .............................................................................................................................. 50
8.2. Polling flowchart .................................................................................................................................... 54
8.3. Ping-pong example ................................................................................................................................ 56
8.4. Memory scatter-gather example ............................................................................................................... 59
8.5. Peripheral scatter-gather example ............................................................................................................ 61
8.6. Memory map for 12 channels, including the alternate data structure ................................................................ 63
8.7. Detailed memory map for the 12 channels, including the alternate data structure ............................................... 64
8.8. channel_cfg bit assignments ................................................................................................................... 65
8.9. 2D copy .............................................................................................................................................. 70
9.1. RMU Reset Input Sources and Connections. .............................................................................................. 99
9.2. RMU Power-on Reset Operation ............................................................................................................ 100
9.3. RMU Brown-out Detector Operation ........................................................................................................ 101
10.1. EMU Overview .................................................................................................................................. 106
10.2. EMU Energy Mode Transitions ............................................................................................................. 107
10.3. Backup power domain overview ........................................................................................................... 112
10.4. Entering and leaving backup mode ....................................................................................................... 113
10.5. BOD calibration using DAC ................................................................................................................. 114
11.1. CMU Overview .................................................................................................................................. 126
11.2. CMU Switching from HFRCO to HFXO before HFXO is ready .................................................................... 129
11.3. CMU Switching from HFRCO to HFXO after HFXO is ready ....................................................................... 130
11.4. HFXO Pin Connection ........................................................................................................................ 130
11.5. LFXO Pin Connection ......................................................................................................................... 131
11.6. HW-support for RC Oscillator Calibration ................................................................................................ 132
11.7. Single Calibration (CONT=0) ................................................................................................................ 132
11.8. Continuous Calibration (CONT=1) ......................................................................................................... 132
13.1. PRS Overview ................................................................................................................................... 163
13.2. TIMER0 overflow starting ADC0 single conversions through PRS channel 5. ................................................. 166
14.1. EBI Overview .................................................................................................................................... 175
14.2. EBI Non-multiplexed 8-bit Data, 8-bit Address Read Operation ................................................................... 176
14.3. EBI Non-multiplexed 8-bit Data, 8-bit Address Write Operation ................................................................... 176
14.4. EBI Address Latch Setup .................................................................................................................... 176
14.5. EBI Multiplexed 16-bit Data, 16-bit Address Read Operation ...................................................................... 177
14.6. EBI Multiplexed 16-bit Data, 16-bit Address Write Operation ...................................................................... 177
14.7. EBI Multiplexed 8-bit Data, 24-bit Address Read Operation ........................................................................ 177
14.8. EBI Multiplexed 8-bit Data, 24-bit Address Write Operation ........................................................................ 178
14.9. EBI Non-multiplexed 16-bit Data Read Operation with Extended Address ...................................................... 178
14.10. EBI Non-multiplexed 16-bit Data Write Operation with Extended Address .................................................... 178
14.11. EBI Page Mode Read Operation for D8A8 addressing mode .................................................................... 179
14.12. EBI Page Mode Read Operation for D16A16ALE addressing mode ............................................................ 180
14.13. EBI Page Mode Read Operation for D8A24ALE addressing mode ............................................................. 180
14.14. EBI Page Mode Read Operation for D16 addressing mode ...................................................................... 180
14.15. EBI Page Closing ............................................................................................................................. 180
14.16. EBI Extended Address Latch Setup ..................................................................................................... 181
14.17. EBI 16-bit Data Multiplexed Read Operation using Extended Addressing ..................................................... 181
14.18. EBI 16-bit Data Multiplexed Write Operation using Extended Addressing ..................................................... 181
14.19. EBI Multiplexed Read Operation with Reduced Length Strobes ................................................................. 183
14.20. EBI Multiplexed Write Operation with Reduced Length Strobes ................................................................. 183
14.21. EBI Enforced IDLE cycles between Transactions ................................................................................... 184
14.22. EBI No Enforced IDLE cycles between Transactions ............................................................................... 184
14.23. EBI Default Memory Map (ALTMAP = 0) .............................................................................................. 186
14.24. EBI Alternative Memory Map (ALTMAP = 1) .......................................................................................... 187
14.25. EBI Connection with Standard NAND Flash .......................................................................................... 188
14.26. EBI Connection with Chip Enable Don't Care NAND Flash ....................................................................... 189
14.27. EBI NAND Flash Command Latch Timing ............................................................................................. 190
14.28. EBI NAND Flash Address Latch Timing ................................................................................................ 190
14.29. EBI NAND Flash Data Input Timing ..................................................................................................... 191
14.30. EBI NAND Flash Data Output Timing .................................................................................................. 192
14.31. EBI ECC Generation ........................................................................................................................ 194
14.32. EBI EBI_ECCPARITY Format ............................................................................................................. 195
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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