EFM32WG Datasheet, PDF (358/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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Bit
Name
Reset
Access Description
Interrupt ensures the core is not reading from the FIFO. USB_GRSTCTL.AHBIDLE ensures the core is not writing anything to the
FIFO. Flushing is normally recommended when FIFOs are reconfigured. FIFO flushing is also recommended during device endpoint
disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear.
4
RXFFLSH
0
RW1
RxFIFO Flush (host and device)
The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The
application must only write to this bit after checking that the core is neither reading from the RxFIFO nor writing to the RxFIFO. The
application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks to clear.
3
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2
FRMCNTRRST
0
RW1
Host Frame Counter Reset (host only)
The application writes this bit to reset the frame number counter inside the core. When the frame counter is reset, the subsequent
SOF sent out by the core has a frame number of 0. When application writes 1 to the bit, it might not be able to read back the value
as it will get cleared by the core in a few clock cycles.
1
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
0
CSFTRST
0
RW1
Core Soft Reset (host and device)
Resets the core by clearing the interrupts and all the CSR registers except the following register bits:
USB_PCGCCTL.RSTPDWNMODULE, USB_PCGCCTL.GATEHCLK, USB_PCGCCTL.PWRCLMP, USB_GUSBCFG.FSINTF,
USB_HCFG.FSLSPCLKSEL, USB_DCFG.DEVSPD.
All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO
are flushed. Any transactions on the AHB Master are terminated as soon as possible, after gracefully completing the last data phase
of an AHB transfer. Any transactions on the USB are terminated immediately. The application can write to this bit any time it wants
to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can
take several clocks, depending on the current state of the core. Once this bit is cleared software must wait at least 3 clock cycles
before doing any access to the core. Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before
starting any operation.
15.6.13 USB_GINTSTS - Interrupt Register
This register interrupts the application for system-level events in the current mode (Device mode or Host
mode). Some of the bits in this register are valid only in Host mode, while others are valid in Device
mode only. This register also indicates the current mode. To clear the interrupt status bits of type RW1,
the application must write 1 into the bit.
The FIFO status interrupts are read only; once software reads from or writes to the FIFO while servicing
these interrupts, FIFO interrupt conditions are cleared automatically.
The application must clear the USB_GINTSTS register at initialization before unmasking the interrupt
bit to avoid any interrupts generated prior to initialization.
Offset
0x3C014
Reset
Bit Position
Access
Name
Bit
Name
Reset
Access Description
31
WKUPINT
0
RW1
Resume/Remote Wakeup Detected Interrupt (host and device)
Wakeup Interrupt during Suspend state. In Device mode this interrupt is asserted only when Host Initiated Resume is detected on
USB. In Host mode this interrupt is asserted only when Device Initiated Remote Wakeup is detected on USB. This bit can be set
only by the core and the application should write 1 to clear.
30
SESSREQINT
0
RW1
Session Request/New Session Detected Interrupt (host and
device)
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
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