EFM32WG Datasheet, PDF (484/834 Pages) List of Unclassifed Manufacturers – The EFM32WG Wonder Gecko is the ideal choice for demanding 8-, 16-, and 32-bit energy sensitive applications.

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17.5.17 USARTn_IF - Interrupt Flag Register
Offset
0x040
Reset
Access
Bit Position
Name
Bit
31:13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Reset
Access Description
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
CCF
0
R
Collision Check Fail Interrupt Flag
Set when a collision check notices an error in the transmitted data.
SSM
0
R
Slave-Select In Master Mode Interrupt Flag
Set when the device is selected as a slave when in master mode.
MPAF
0
R
Multi-Processor Address Frame Interrupt Flag
Set when a multi-processor address frame is detected.
FERR
0
R
Framing Error Interrupt Flag
Set when a frame with a framing error is received while RXBLOCK is cleared.
PERR
0
R
Parity Error Interrupt Flag
Set when a frame with a parity error (asynchronous mode only) is received while RXBLOCK is cleared.
TXUF
0
R
TX Underflow Interrupt Flag
Set when operating as a synchronous slave, no data is available in the transmit buffer when the master starts transmission of a
new frame.
TXOF
0
R
TX Overflow Interrupt Flag
Set when a write is done to the transmit buffer while it is full. The data already in the transmit buffer is preserved.
RXUF
0
R
RX Underflow Interrupt Flag
Set when trying to read from the receive buffer when it is empty.
RXOF
0
R
RX Overflow Interrupt Flag
Set when data is incoming while the receive shift register is full. The data previously in the shift register is lost.
RXFULL
0
R
RX Buffer Full Interrupt Flag
Set when the receive buffer becomes full.
RXDATAV
0
R
RX Data Valid Interrupt Flag
Set when data becomes available in the receive buffer.
TXBL
1
R
TX Buffer Level Interrupt Flag
Set when buffer becomes empty if TXBIL is set, or when buffer goes from full to half-full if TXBIL is cleared.
TXC
0
R
TX Complete Interrupt Flag
This interrupt is used after a transmission when both the TX buffer and shift register are empty.
2013-05-08 - Wonder Gecko Family - d0233_Rev0.50
484
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